Texas Instruments TPS7A6050EVM Evaluation Module TPS7A6050EVM TPS7A6050EVM Datenbogen
Produktcode
TPS7A6050EVM
www.ti.com
Board Layout
2.3
Operation
The TPS7A6050QKTT will power-up after the V
BAT
voltage has exceeded the Power-On Reset threshold.
The DELAY jumper should be configured for the desired nRST delay time.
In this configuration, the device will power up when power is applied.
The PCB offers footprints for the TPS7A6050QKTTQ1 or the TPS7A6050QKVUQ1 device.
3
Board Layout
, and
show the board layout for the TPS7A6050QKTT EVM PWB. The EVM
offers capacitors and a jumper to program the nRST delay time.
The PowerPAD™ package offers an exposed thermal pad to enhance thermal performance. This must be
soldered to the copper landing on the PCB for optimal performance. The PCB provides 2 oz copper
planes on the top and bottom to dissipate heat.
soldered to the copper landing on the PCB for optimal performance. The PCB provides 2 oz copper
planes on the top and bottom to dissipate heat.
Figure 2. Top Assembly Layer
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SLVU397 – August 2010
TPS7A6050QKTT EVM
Copyright © 2010, Texas Instruments Incorporated