Texas Instruments TPS54339E Evaluation Module TPS54339EEVM-056 TPS54339EEVM-056 Datenbogen
Produktcode
TPS54339EEVM-056
V
= 1 V / div
OUT
Time = 2 msec / div
EN = 10 V / div
V = 10 V / div
IN
SS = 5 V / div
Board Layout
Figure 14. TPS54339EEVM-056 Shut-Down Relative to EN with SS
5
Board Layout
This section provides description of the TPS54339EEVM-056, board layout, and layer illustrations.
5.1
Layout
The board layout for the TPS54339EEVM-056 is shown in
through
. The top layer
contains the main power traces for VIN, VO, and ground. Also on the top layer are connections for the
pins of the TPS54339E and a large area filled with ground. Many of the signal traces also are located on
the top side. The input decoupling capacitors are located as close to the IC as possible. The input and
output connectors, test points, and all of the components are located on the top side. An analog ground
(GND) area is provided on the top side. Analog ground (GND) and power ground (PGND) are connected
at a single point on the top layer near C6. The two internal layers are completely dedicated to power
ground planes. The bottom layer is primarily power ground. A copper pour area on the bottom layer is
used to connect the switching node (SW) to the output inductor and the boost capacitor. Traces also
connect enable control jumper, EN, VREG5, and LOOP test points, and the feedback trace from VOUT to
the voltage setpoint divider network.
pins of the TPS54339E and a large area filled with ground. Many of the signal traces also are located on
the top side. The input decoupling capacitors are located as close to the IC as possible. The input and
output connectors, test points, and all of the components are located on the top side. An analog ground
(GND) area is provided on the top side. Analog ground (GND) and power ground (PGND) are connected
at a single point on the top layer near C6. The two internal layers are completely dedicated to power
ground planes. The bottom layer is primarily power ground. A copper pour area on the bottom layer is
used to connect the switching node (SW) to the output inductor and the boost capacitor. Traces also
connect enable control jumper, EN, VREG5, and LOOP test points, and the feedback trace from VOUT to
the voltage setpoint divider network.
12
TPS54339EEVM-056, 3-A, Regulator with Eco-Mode™ Evaluation Module
SLVU814 – November 2012
Copyright © 2012, Texas Instruments Incorporated