Texas Instruments DRV2605EVM-CT Datenbogen
W
Start
condition
I
2
C device address
and R/W bit
Subaddress
Acknowledge
Acknowledge
Acknowledge
R
Acknowledge
First data byte
Repeat start
condition
I
2
C device address
and R/W bit
Stop
condition
Acknowledge
Acknowledge
Other data byte
Last data byte
A6
A0
ACK A7
A6
A1
A0 ACK
A6
A5
A0
ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
A6
A5
A1
A0
W
A7
A6
A1
A0
A6
A5
D0
Stop
Condition
Start
Condition
I
2
C device address and
R/W bit
Subaddress
Acknowledge
Acknowledge
Acknowledge
A0
R
Acknowledge
D7
Data Byte
Repeat start
condition
I
2
C device address and
R/W bit
ACK
ACK
ACK
ACK
Stop
condition
Start
condition
I
2
C device address
and R/W bit
Subaddress
First data byte
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Other data bytes
Acknowledge
Last data byte
D0
ACK D7
D0
ACK
D0
ACK D7
D1
ACK
D7
D6
A0
A1
ACK
A7
A6
W
A0
A1
A0
A1
SLOS825C – DECEMBER 2012 – REVISED SEPTEMBER 2014
Programming (continued)
7.5.3.5 Multiple-Byte Write and Incremental Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DRV2605 device as shown in
are transmitted by the master device to the DRV2605 device as shown in
. After receiving each data
byte, the DRV2605 device responds with an acknowledge bit.
Figure 20. Multiple-Byte Write Transfer
7.5.3.6 Single-Byte Read
shows that a single-byte data-read transfer begins with the master device transmitting a start condition
followed by the I
2
C device address and the read-write bit. For the data-read transfer, both a write followed by a
read actually occur. Initially, a write occurs to transfer the address byte of the internal memory address to be
read. As a result, the read-write bit is set to 0.
read. As a result, the read-write bit is set to 0.
After receiving the DRV2605 address and the read-write bit, the DRV2605 device responds with an acknowledge
bit. The master then sends the internal memory address byte, after which the device issues an acknowledge bit.
The master device transmits another start condition followed by the DRV2605 address and the read-write bit
again. This time, the read-write bit is set to 1, indicating a read transfer. Next, the DRV2605 device transmits the
data byte from the memory address that is read. After receiving the data byte, the master device transmits a not-
acknowledge followed by a stop condition to complete the single-byte data read transfer. See the note in the
bit. The master then sends the internal memory address byte, after which the device issues an acknowledge bit.
The master device transmits another start condition followed by the DRV2605 address and the read-write bit
again. This time, the read-write bit is set to 1, indicating a read transfer. Next, the DRV2605 device transmits the
data byte from the memory address that is read. After receiving the data byte, the master device transmits a not-
acknowledge followed by a stop condition to complete the single-byte data read transfer. See the note in the
section.
Figure 21. Single-Byte Read Transfer
7.5.3.7 Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the DRV2605 device to the master device as shown in
are transmitted by the DRV2605 device to the master device as shown in
. With the exception of the
last data byte, the master device responds with an acknowledge bit after receiving each data byte.
Figure 22. Multiple-Byte Read Transfer
Copyright © 2012–2014, Texas Instruments Incorporated
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