Texas Instruments TPS65290 Ultra-Low Power Management Unit Evaluation Module TPS65290LMEVM TPS65290LMEVM Datenbogen
Produktcode
TPS65290LMEVM
Introduction
1
Introduction
1.1
I/O Description
Table 1. Power Connection
NUMBER
TYPE
LOCATION
SIGNAL
COMMENT
J1
I
N
Input supply
Connection to input supply
J2
I
N
SPI
Connection to SPI interface board
J3
O
S
LDO and MICRO outputs
Connection to MICRO and LDO output
J7
O
E
Buck-boost output
Connection to buck-boost output
Table 2. Header Descriptions
NUMBER
FUNCTION
LOCATION
PLACEMENT
COMMENT
Connect analog VIN(pin #2) to the
JP1
Supply connect
NW
Fit in most cases
main power connector(J1)
Connect VMAX to the joint of 1µF and
JP4
LDO input connector
W
Fit in most cases
LDO input
Fit only when Buck mini is
JP8
Buck mini connection
S
Connection to Buck mini inductor
used
Connection to PWR_LDO2 output If
Not connect in BUCKmini
JP8A
PWR_LDO2 connector
S
buck-mini option available leave open
mode
When not fitted adds a 1-
Ω
resistance
to the output capacitor, allowing for a
Fit according to test
JP10
Buck MINI output ESR
S
predictable ESR value for the
requirement
BUCKmini mode. Fit for low IQQ LDO
or zero leak circuit.
or zero leak circuit.
Connect to VMICRO for enabling
serial communication. Conect to GND
serial communication. Conect to GND
Fit according to test
JP11
CE
S
for Vmicro only mode for lowest IDDQ requirement
consumption.
consumption.
Connect to GND to disable BB (I2C
Fit according to test
JP13
BB enable
SE
can enable it). Connect to VMICRO to
requirement
enable BB.
3
SLVU906 – April 2013
Low IDDQ PMIC for Battery Energy Harvesting Applications
Copyright © 2013, Texas Instruments Incorporated