Texas Instruments TPS728185315EVM267 Evaluation Module TPS728185315EVM267 TPS728185315EVM267 Datenbogen
Produktcode
TPS728185315EVM267
www.ti.com
2.1
Test Setup
2.2
Test Results
Time (100 s
)
m
/div
V
Transitioning from 3.15V to 1.85V
I
= 1mA
OUT
OUT
V
OUT
V
SET
200mV
/div
Time (10 s
)
m
/div
V
Transition Time < 40 s (2% settling)
m
OUT
V
OUT
V
SET
V
Transitioning from 1.85V to 3.15V
I
= 1mA
OUT
OUT
200mV
/div
Time (40 s
)
m
/div
V
Transitioning from 1.85V to 3.15V
I
= 10mA
OUT
OUT
V
OUT
V
SET
V
Transition Time < 40 s (2% settling)
m
OUT
200mV
/div
Time (20 s/div)
m
V
Transitioning from 3.15V to 1.85V
I
= 10mA
OUT
OUT
V
OUT
V
SET
200mV
/div
Input/Output Connector Descriptions
TP2 – Test point for measuring V
OUT
for the QFN (DRV) packaged device.
TP3 – Test point for measuring board ground.
TP4 – Test point for measuring V
IN
for the chipscale (YZU) packaged device.
TP5 – Test point for measuring V
OUT
for the chipscale (YZU) packaged device.
The maximum recommended voltage allowed on the IN terminal is 6.5V with the maximum on EN or
VSET being V
VSET being V
IN
. Headers J1 and J5 are not connected. So, connect the positive side of separate or one
input power supply to headers J1 and J5 and the negative (ground) side header J3. To enable the QFN
(DRV) packaged regulator, place JP1 in the ON postion. To enable the chipscale (YZU) packaged
regulator, place JP4 in the ON postion. Use JP2 or JP3 to change the output voltage of the DRV and YZU
packages respectively, between VOUT1 =1.85V and VOUT2 = 3.15V. When connecting the positive side
of external loads to either header J2 or J6 and the negative (ground) side to header J4, use short, twisted
leads in order to minimize DC drop at the connector and/or inductive voltage dip after a transient load is
removed. Additional input capacitance may be required if the input power supply is connected to the
boards via long leads and/or fast load transients are applied to the output.
(DRV) packaged regulator, place JP1 in the ON postion. To enable the chipscale (YZU) packaged
regulator, place JP4 in the ON postion. Use JP2 or JP3 to change the output voltage of the DRV and YZU
packages respectively, between VOUT1 =1.85V and VOUT2 = 3.15V. When connecting the positive side
of external loads to either header J2 or J6 and the negative (ground) side to header J4, use short, twisted
leads in order to minimize DC drop at the connector and/or inductive voltage dip after a transient load is
removed. Additional input capacitance may be required if the input power supply is connected to the
boards via long leads and/or fast load transients are applied to the output.
shows the test results at T
A
= 25
°
C using this EVM:
Figure 1. VSET Toggled Low to High,
Figure 2. VSET Toggled High to Low,
I
OUT
= 1 mA
I
OUT
= 1 mA
Figure 3. VSET Toggled Low to High,
Figure 4. VSET Toggled High to Low,
I
OUT
= 10 mA
I
OUT
= 10 mA
SLVU212 – October 2007
TPS728185315EVM-267
3