Texas Instruments Evaluation Module for TPS24711 Positive Voltage, Power-Limiting Hotswap Controller TPS24711EVM-004 TPS24711EVM-004 Datenbogen
Produktcode
TPS24711EVM-004
LIM
PROG
SENSE
3125
P
R
R
=
´
SLVSAL2E – JANUARY 2011 – REVISED NOVEMBER 2013
–
V
VCC
drops below the UVLO threshold
2. GATE is pulled down by a 1 A current source for 13.5 µs when a hard output short circuit occurs and
V
(VCC – SENSE)
is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is
complete, an 11-mA sustaining current ensures that the external MOSFET remains off.
3. GATE is discharged by a 20 k
Ω resistor to GND if the chip die temperature exceeds the OTSD rising
threshold.
GATE remains low in latch mode (TPS24710/12) and attempts a restart periodically in retry mode
(TPS24711/13).
(TPS24711/13).
If used, any capacitor connecting GATE and GND should not exceed 1
μF and it should be connected in series
with a resistor of no less than 1 k
Ω. No external resistor should be directly connected from GATE to GND or from
GATE to OUT.
GND: This pin is connected to system ground.
OUT: This pin allows the controller to measure the drain-to-source voltage across the external MOSFET M
1
. The
power-good indicator (PG/PGb) relies on this information, as does the power limiting engine. The OUT pin should
be protected from negative voltage transients by a clamping diode or sufficient capacitors. A Schottky diode of
3 A / 40 V in a SMC package is recommended as a clamping diode for high-power applications. The OUT pin
should be bypassed to GND with a low-impedance ceramic capacitor in the range of 10 nF to 1
be protected from negative voltage transients by a clamping diode or sufficient capacitors. A Schottky diode of
3 A / 40 V in a SMC package is recommended as a clamping diode for high-power applications. The OUT pin
should be bypassed to GND with a low-impedance ceramic capacitor in the range of 10 nF to 1
μF.
PG: PG is assigned for TPS24712/13. This active-high, open-drain output is intended to interface to downstream
dc/dc converters or monitoring circuits. PG assumes high-impedance after the drain-to-source voltage of the FET
has fallen below 170 mV and a 3.4-ms deglitch delay has elapsed. It pulls low when V
dc/dc converters or monitoring circuits. PG assumes high-impedance after the drain-to-source voltage of the FET
has fallen below 170 mV and a 3.4-ms deglitch delay has elapsed. It pulls low when V
DS
exceeds 240 mV. PG
assumes low-impedance status after a 3.4-ms deglitch delay once V
DS
of M
1
rises up, resulting from GATE being
pulled to GND at any of the following conditions:
•
•
An overload current fault occurs (V
SENSE
> 25 mV).
•
A hard output short circuit occurs, leading to V
(VCC – SENSE)
greater than 60 mV, i.e., the fast-trip shutdown
threshold has been exceeded.
•
V
EN
is below its falling threshold.
•
V
VCC
drops below the UVLO threshold.
•
Die temperature exceeds the OTSD threshold.
This pin can be left floating when not used.
PGb: PGb is assigned for TPS24710/11. This active-low, open-drain output is intended to interface to
downstream dc/dc converters or monitoring circuits. PGb pulls low after the drain-to-source voltage of the FET
has fallen below 170 mV and a 3.4-ms deglitch delay has elapsed. It goes open-drain when VDS exceeds 240
mV. PGb assumes high-impedance status after a 3.4-ms deglitch delay once V
downstream dc/dc converters or monitoring circuits. PGb pulls low after the drain-to-source voltage of the FET
has fallen below 170 mV and a 3.4-ms deglitch delay has elapsed. It goes open-drain when VDS exceeds 240
mV. PGb assumes high-impedance status after a 3.4-ms deglitch delay once V
DS
of M
1
rises up, resulting from
GATE being pulled to GND at any of the following conditions:
•
•
An overload current fault occurs (V
SENSE
> 25 mV).
•
A hard output short circuit occurs, leading to V
(VCC – SENSE)
greater than 60 mV, i.e., the fast-trip shutdown
threshold has been exceeded.
•
V
EN
is below its falling threshold.
•
V
VCC
drops below the UVLO threshold.
•
Die temperature exceeds the OTSD threshold.
This pin can be left floating when not used.
PROG: A resistor from this pin to GND sets the maximum power permitted in the external MOSFET M
1
during
inrush. Do not apply a voltage to this pin. If the constant power limit is not desired, use a PROG resistor of
4.99 k
4.99 k
Ω. To set the maximum power, use
,
(1)
where P
LIM
is the allowed power limit of MOSFET M
1
. R
SENSE
is the load-current-monitoring resistor connected
between the VCC pin and the SENSE pin. R
PROG
is the resistor connected from the PROG pin to GND. Both
R
PROG
and R
SENSE
are in ohms and P
LIM
is in watts. P
LIM
is determined by the maximum allowed thermal stress of
MOSFET M
1
, given by
8
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