Texas Instruments CDCE949Perf-EVM - CDCE949 Performance Evaluation Module CDCE949PERF-EVM CDCE949PERF-EVM Datenbogen
Produktcode
CDCE949PERF-EVM
ƒ
OUT
+
ƒ
IN
Pdiv
N
M
ƒ
VCO
+
ƒ
IN
N
M
)
M
N
int(log
4
P
2
-
=
)
M
'
N
int(
Q =
Q
M
'
N
R
´
-
=
www.ti.com
SCAS844D – AUGUST 2007 – REVISED MARCH 2010
PLL MULTIPLIER/DIVIDER DEFINITION
At a given input frequency (f
IN
), the output frequency (f
OUT
) of the CDCE949/CDCEL949 can be calculated by:
where
M (1 to 511) and N (1 to 4095) are the multiplier/divider values of the PLL;
Pdiv (1 to 127) is the output divider.
Pdiv (1 to 127) is the output divider.
The target VCO frequency (f
VCO
) of each PLL can be calculated:
The PLL operates as fractional divider and needs following multiplier/divider settings
N
{if P < 0 then P = 0}
Where:
N' = N × 2
P
;
N
≥
M;
80 MHz < f
VCO
> 230 MHz;
16
≤
q
≤
63;
0
≤
p
≤
7;
0
≤
r
≤
511.
Example 1: for f
IN
= 27 MHz; M = 1; N = 4; Pdiv = 2;
Example 2: for f
IN
= 27 MHz; M = 2; N = 11; Pdiv = 2;
→
f
OUT
= 54 MHz;
→
f
OUT
= 75.25 MHz;
→
f
VCO
= 108 MHz;
→
f
VCO
= 148.50 MHz;
→
P = 4 – int(log
2
4) = 4 –2 = 2;
→
P = 4 – int(log
2
5.5) = 4 – 2 = 2;
→
N’ = 4 × 2
2
= 16;
→
N’ = 11 × 2
2
= 44;
→
Q = int(16) = 16;
→
Q = int(22) = 22;
→
R = 16 – 16 = 0;
→
R = 44 – 44 = 0;
The values for P, Q, R and N’ are automatically calculated when using TI Pro Clock™ Software.
Copyright © 2007–2010, Texas Instruments Incorporated
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