Texas Instruments TPS56921 Synchronous Step-Down Converter Evaluation Module TPS56921EVM-188 TPS56921EVM-188 Datenbogen
Produktcode
TPS56921EVM-188
0
10
20
30
40
50
60
70
80
90
100
0
1
2
3
4
5
6
7
8
9
E
ff
ici
e
n
cy
-
%
Output Current - A
C001
V
IN
= 5 V
V
IN
= 12 V
Test Setup and Results
Table 4. EVM Connectors and Test Points
Reference Designator
Function
J1
VIN input voltage connector. Not normally used.
J2
PVIN input voltage connector. (See
for V
IN
range.)
J3
I
2
C interface connector.
J4
V
OUT
, 1.1 V at 9 A maximum
JP1
PVIN to VIN jumper. Normally closed to tie VIN to PVIN for common rail voltage operation.
JP2
2-pin header for enable. Connect EN to ground to disable, open to enable.
JP3
I
2
C interface pull up jumper for SDA.
JP4
I
2
C interface pull up jumper for SCL.
JP5
I
2
C interface grounding jumper for A0.
JP6
I
2
C interface grounding jumper for A1.
JP7
PWRGD pull up to Vin.
(1)
TP1
VIN test point at VIN connector.
TP2
GND test point at VIN connector.
TP3
PVIN test point at PVIN connector.
TP4
GND test point at PVIN connector.
TP5
PWRGD test point.
TP6
PH test point.
TP7
COMP pin test point.
TP8
Analog GND test point.
Test point in voltage divider network at VO. Used for loop response measurements when output voltage
TP9
is set using I
2
C control.
Test point in voltage divider network. Used for loop response measurements when output voltage is set
TP10
using external resistor divider network.
TP11
Output voltage test point at VOUT connector.
TP12
GND test point at VOUT connector.
(1)
Absolute maximum voltage for PWRGD is 6 V. Do not use JP7 to connect to VIN for input voltages above 6 V.
2.2
Efficiency
shows the efficiency for the TPS56921EVM-188 at an ambient temperature of 25°C.
Figure 1. TPS56921EVM-188 Efficiency
5
SLVU793 – October 2012
TPS56921EVM-188, 9-A, SWIFT™ Regulator Evaluation Module
Copyright © 2012, Texas Instruments Incorporated