Texas Instruments Clock Jitter Cleaner With Cascaded PLLs and Integrated 1.6 GHz VCO (LVPECL LVCMOS Outputs) LMK04002BEV LMK04002BEVAL/NOPB Datenbogen
Produktcode
LMK04002BEVAL/NOPB
16 SNAU045A
LMK040xx Evaluation Board User’s Guide
November 2013
Copyright © 2013, Texas Instruments Incorporated
www.ti.com
Evaluation Board Kit Contents
The evaluation board is typically shipped with a parallel port cable that is used to interconnect the board to a PC
USB or LPT port, enabling the board to be programmed. The kit may also include one or more BALUN boards.
Each BALUN board is configured to accept a differential signal input and provide a single-ended signal output. This
enables the differential clock outputs of the LMK040xxB to be connected to test equipment or to drive single-ended
circuits. The user should be aware that there is some attenuation of the clock signal when using these boards.
Please see also “EVM Software and Communication: Interfacing u-Wire” for more information).
Appendix contains typical frequency response data for the BALUN boards.
NOTE: If the board contains an ADT2-1T BALUN, DC bias on the input signals is blocked at the output. If
the board contains an ADTL2-18, DC bias on the input will be passed to the output. This may be
unacceptable for some types of test equipment.
PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded PLL architecture, the first PLL affectively substitutes the phase
noise of a low noise oscillator (VCXO or crystal resonator) for the phase noise of a “dirty” reference clock. The first
PLL is typically configured with a narrow loop bandwidth in order to minimize the impact of the reference clock
phase noise. The reference clock consequently serves only as a frequency reference rather than a phase
reference. If the jitter of the VCXO is superior to that of the reference clock, the loop bandwidth of the second PLL
can be made much wider relative to the first PLL.
The loop filters on the LMK040xx evaluation board are setup using this approach. The loop filter for PLL1 has been
configured for a narrow loop bandwidth (< 100 Hz), while the loop filter of PLL2 has been configured for a wide loop
bandwidth (> 50 kHz). The specific loop bandwidth values depend on the phase noise performance of the oscillator
mounted on the board. The following tables contain the parameters for PLL1 and PLL2 for each oscillator option.
Texas Instruments Incorporated’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given
PLL1 and PLL2 Parameters for Crystal Mode operating with a 12.288 MHz XTAL.
XTAL OSC Option PLL 1 Loop Filter
Phase Margin
61º
100 uA
Loop Bandwidth
10 Hz
Fcomp
1024 kHz
Ref Clk Frequency
122.88 MHz
Output Frequency
12.288 MHz
(To PLL 2)
Supply Voltage
3.3 Volts
VCO Gain
1.5 kHz/Volt
Loop Filter
Components
C1 = 330 nF
C2 = 10 uF
R2 = 3.9k ohms
XTAL Option PLL 2 Loop Filter
Phase Margin
66º
1600 uA
Loop Bandwidth
54 kHz
Fcomp
12.288 MHz
Crystal Frequency
12.228 MHz
(From PLL1)
Output Frequency
1474.56 MHz