Texas Instruments BQ2022A Evaluation Module BQ2022AEVM-001 BQ2022AEVM-001 Datenbogen

Produktcode

BQ2022AEVM-001

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SDQI

SDQO

VSS

Communications

Controller

CPU

HOST

bq2022 A

VPU

VSS

SDQ

Serial Communication

Initialization

ROM COMMANDS

READ ROM

CRC (1 BYTE)

Reset

and

Presence

Signals

Read ROM (33h)

Family Code and Identification

Number (7 BYTES)

bq2022A

SLUS724C – SEPTEMBER 2006 – REVISED AUGUST 2007

Figure 1. Typical Applications Circuit

A host reads, programs, or checks the status of the bq2022A through the hierarchical command structure of the
SDQ interface.

Figure 2

shows that the host must first issue a ROM command before the EPROM memory or

status can be read or modified. The ROM command either selects a specific device when multiple devices are on
the SDQ bus, or skips the selection process in single SDQ device applications.

Initialization

ROM Command Sequence

Memory/Status Command Sequence

Figure 2. General Command SequenceFigure

Initialization consists of two pulses, the RESET and the PRESENCE pulses. The host generates the RESET
pulse, while the bq2022A responds with the PRESENCE pulse. The host resets the bq2022A by driving the
DATA bus low for at least 480

s. For more details, see the RESET section under SDQ Signaling.

The READ ROM command sequence is the fastest sequence that allows the host to read the 8-bit family code
and 48-bit identification number. It is used if only one SDQ slave device is attached to the bus. The READ ROM
sequence starts with the host generating the RESET pulse of at least 480

s. The bq2022A responds with a

PRESENCE pulse. Next, the host continues by issuing the READ ROM command, 33h, and then reads the ROM
and CRC byte using the READ signaling (see the READ and WRITE signals section) during the data frame.

Figure 3. READ ROM Sequence

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