Texas Instruments LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input LMK00101BEVAL/NOP LMK00101BEVAL/NOPB Datenbogen
Produktcode
LMK00101BEVAL/NOPB
4 LMK00101 Users Guide
SNLU098
3. Signal Path and Control Switches
The LMK00101 supports single-ended or differential clocks on CLKin0 and CLKin1. A third input, OSCin, has
an integrated crystal oscillator interface that supports a fundamental mode, AT-cut crystal or an external single-
ended clock. The three-input multiplexer is pin-controlled. To achieve the maximum operating frequency and
lowest additive jitter, it is recommended to use a differential clock with high input slew rate (>1 V/ns) and DC-
coupling to either CLKin0 or CLKin1 port.
All control pins are configured with the control switch, S3. The output enable logic is shown in
an integrated crystal oscillator interface that supports a fundamental mode, AT-cut crystal or an external single-
ended clock. The three-input multiplexer is pin-controlled. To achieve the maximum operating frequency and
lowest additive jitter, it is recommended to use a differential clock with high input slew rate (>1 V/ns) and DC-
coupling to either CLKin0 or CLKin1 port.
All control pins are configured with the control switch, S3. The output enable logic is shown in
Table 4:
Output Enable Selection (0=OFF, 1=ON)
CLKout Enable Mode
S1[3] - OE
Disabled/Hi-Z
0
Enabled
1
4. Power Supplies
By default, Vdd and VddCLKout are supplied by two external power supplies. To modify the EVK
with a different power supply configuration, populate the resistor options as shown in Table 5. Then,
apply the appropriate voltage(s) to the EVK power input(s).
Decoupling capacitors and 0-ohm resistor footprints, which can accommodate ferrite beads, can be
used to isolate the EVK power input(s) from the device power pins. Do not disconnect or ground any
of the VddCLKout pins as they are all internally connected inside the device.
with a different power supply configuration, populate the resistor options as shown in Table 5. Then,
apply the appropriate voltage(s) to the EVK power input(s).
Decoupling capacitors and 0-ohm resistor footprints, which can accommodate ferrite beads, can be
used to isolate the EVK power input(s) from the device power pins. Do not disconnect or ground any
of the VddCLKout pins as they are all internally connected inside the device.
Table 5: Power Supply Configuration
Dual Ext. Inputs
(Default)
Single Ext. Input
3.3 V
Vdd input
Apply 3.3 V
Apply 3.3 V ± 5%
VddCLKout input
Apply Voltage ≤ Vdd
Not used
R38
0 Ohm
DNP
R39
0 Ohm
0 Ohm
R43
DNP
0 Ohm
5. Clock Inputs
The SMA inputs labeled CLKin0 & CLKin0* and CLKin1 & CLKin1* are configured to receive
a differential clock or single-ended clock. Best performance is achieved with a DC-coupled
differential input clock.
a differential clock or single-ended clock. Best performance is achieved with a DC-coupled
differential input clock.
5.1 Crystal Oscillator Interface
The LMK00101 has an integrated crystal oscillator interface (OSCin/OSCout) that supports a
fundamental mode, AT-cut crystal. If the crystal input is selected, an optional onboard XTAL on
either footprint Y1 or Y2 will start-up and the oscillator clock can be measured on any enabled
output.
fundamental mode, AT-cut crystal. If the crystal input is selected, an optional onboard XTAL on
either footprint Y1 or Y2 will start-up and the oscillator clock can be measured on any enabled
output.