Texas Instruments LMK01000 Evaluation Board LMK01000EVAL/NOPB LMK01000EVAL/NOPB Datenbogen
Produktcode
LMK01000EVAL/NOPB
SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009
•
Program R0 to R7 as necessary with desired clocks with appropriate enable, mux, divider, and delay settings.
•
Program R14 with global clock output bit, power down setting.
–
–
R14 must be programmed in accordance with the register map as shown in the register map (See Section
2.2).
2.2).
Table 1. Register Map
Re
gis
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ter
Data [27:0]
A3
A2
A1
A0
CL
RE
CLKout0
Ko
CLKout0_DIV
CLKout0_DLY
R0
SE
0
0
0
0
0
0
0
0
0
0
0
0
_MUX
ut0
0
0
0
0
[7:0]
[3:0]
T
[1:0]
_E
N
CL
CLKout1
Ko
CLKout1_DIV
CLKout1_DLY
R1
0
0
0
0
0
0
0
0
0
0
0
0
0
_MUX
ut1
0
0
0
1
[7:0]
[3:0]
[1:0]
_E
N
CL
CLKout2
Ko
CLKout2_DIV
CLKout2_DLY
R2
0
0
0
0
0
0
0
0
0
0
0
0
0
_MUX
ut2
0
0
1
0
[7:0]
[3:0]
[1:0]
_E
N
CL
CLKout3
Ko
CLKout3_DIV
CLKout3_DLY
R3
0
0
0
0
0
0
0
0
0
0
0
0
0
_MUX
ut3
0
0
1
1
[7:0]
[3:0]
[1:0]
_E
N
CL
CLKout4
Ko
CLKout4_DIV
CLKout4_DLY
R4
0
0
0
0
0
0
0
0
0
0
0
0
0
_MUX
ut4
0
1
0
0
[7:0]
[3:0]
[1:0]
_E
N
CL
CLKout5
Ko
CLKout5_DIV
CLKout5_DLY
R5
0
0
0
0
0
0
0
0
0
0
0
0
0
_MUX
ut5
0
1
0
1
[7:0]
[3:0]
[1:0]
_E
N
CL
CLKout6
Ko
CLKout6_DIV
CLKout6_DLY
R6
0
0
0
0
0
0
0
0
0
0
0
0
0
_MUX
ut6
0
1
1
0
[7:0]
[3:0]
[1:0]
_E
N
CL
CLKout7
Ko
CLKout7_DIV
CLKout7_DLY
R7
0
0
0
0
0
0
0
0
0
0
0
0
0
_MUX
ut7
0
1
1
1
[7:0]
[3:0]
[1:0]
_E
N
Vb
R9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
o
0
0
1
0
1
0
1
0
0
0
0
0
1
0
0
1
ost
EN
CL
PO
_C
Kin
W
LK
R1
_S
ER
0
1
0
out
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
4
EL
DO
_G
EC
W
lob
T
N
al
REGISTER R0 to R7
Registers R0 through R7 control the eight clock outputs. Register R0 controls CLKout0, Register R1 controls
CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the functions of
these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the
actual clock output which may be from 0 to 7.
CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the functions of
these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the
actual clock output which may be from 0 to 7.
Table 2. Default Register Settings after Power-on-Reset
Default
Bit
Bit Name
Bit State
Bit Description
Register
Bit Value
Location
RESET
0
No reset, normal operation
Reset to power on defaults
R0
31
Copyright © 2008–2009, Texas Instruments Incorporated
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