Texas Instruments LMK04131 Clock Jitter Cleaner with Cascade PLL LMK04131EVAL/NOPB LMK04131EVAL/NOPB Datenbogen
Produktcode
LMK04131EVAL/NOPB
L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
SNLU099
15
Appendix B: Typical Phase Noise Performance Plots
PLL1
The LMK041xx‟s two stage jitter cleaning process involves masking the reference noise with a
VCXO or Crystal. Therefore the phase noise performance of the VCXO or Crystal of PLL1 is a
very important contributor to the final phase noise of the system.
VCXO or Crystal. Therefore the phase noise performance of the VCXO or Crystal of PLL1 is a
very important contributor to the final phase noise of the system.
Crystek 122.88 MHz VCXO
The phase noise of the reference is masked by the phase noise of this VCXO by using a narrow
loop bandwidth. This VCXO sets the reference noise to PLL2. Figure 7 shows the open loop
typical phase noise performance of the CVHD-950-122.88 Crystek VCXO.
loop bandwidth. This VCXO sets the reference noise to PLL2. Figure 7 shows the open loop
typical phase noise performance of the CVHD-950-122.88 Crystek VCXO.
Figure 7 - CVHD-950-122.88 MHz VCXO Phase Noise at 122.88 MHz
Table 3 - VCXO Phase Noise
at 122.88 MHz (dBc/Hz)
Offset
Phase
Noise
10 Hz
-76.6
100 Hz
-108.9
1 kHz
-137.4
10 kHz
-153.3
100 kHz
-162.0
1 MHz
-165.7
10 MHz
-168.1
40 MHz
-168.1
Table 4 - VCXO RMS Jitter
to high offset of 20 MHz
at 122.88 MHz (rms fs)
Low
Offset
Jitter
10 Hz
515.4
100 Hz
60.5
1 kHz
36.2
10 kHz
35.0
100 kHz
34.5
1 MHz
32.9
10 MHz
22.7
VCXO Phase Noise
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
10
100
1000
10000
100000
1000000 10000000
1E+08
Offset (Hz)
P
h
a
s
e
N
o
is
e
(
d
B
c
/H
z)
CVHD-950-122.88