Texas Instruments LMK04131 Clock Jitter Cleaner with Cascade PLL LMK04131EVAL/NOPB LMK04131EVAL/NOPB Datenbogen
Produktcode
LMK04131EVAL/NOPB
L M K 0 4 1 X X - R E V 3 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
SNLU099
39
Appendix H: LMK04100
The block diagram in Figure 20 illustrates the functional architecture of the LMK041xx clock
conditioner. It features a cascaded, dual PLL arrangement, available internal loop filter
components for PLL2, internal VCO with PLL2 for frequency synthesis, and clock distribution
section with individual clock output dividers and delay adjustment blocks. The dual reference
clock input to PLL1 provides fail-safe redundancy for phase locked loop operation. The cascaded
PLL architecture allows PLL1 to be used as a jitter cleaner for an incoming reference clock that
contains excessive phase noise. This requires the user to select an external oscillator (VCXO or
crystal) that provides the desired phase noise performance at the clock output. This external
oscillator becomes the reference clock for PLL2 and along with the phase noise characteristics of
PLL2 and the internal VCO, determines the final phase noise performance at FOUT and the
output of the clock distribution section.
conditioner. It features a cascaded, dual PLL arrangement, available internal loop filter
components for PLL2, internal VCO with PLL2 for frequency synthesis, and clock distribution
section with individual clock output dividers and delay adjustment blocks. The dual reference
clock input to PLL1 provides fail-safe redundancy for phase locked loop operation. The cascaded
PLL architecture allows PLL1 to be used as a jitter cleaner for an incoming reference clock that
contains excessive phase noise. This requires the user to select an external oscillator (VCXO or
crystal) that provides the desired phase noise performance at the clock output. This external
oscillator becomes the reference clock for PLL2 and along with the phase noise characteristics of
PLL2 and the internal VCO, determines the final phase noise performance at FOUT and the
output of the clock distribution section.
Figure 20 - Functional Block Diagram of the LMK041xx Dual PLL Precision Clock Conditioner with
External VCXO module.
PLL2
PLL1
R
1
Dq
1
N
1
R
2
N
2
Dq
2
VCO
CLKin0
CLKin1
VCO
DIV
CHAN
DIV
D
CHAN
DIV
D
5 Output Clock
Channels
LVPECL, LVDS,
LVCMOS
F
OUT
CLKout_0
CLKout_4
uWire
Interface
DATA
CLK
LE
vcxo