Texas Instruments DAC8560EVM - DAC8560EVM Evaluation Module DAC8560EVM DAC8560EVM Datenbogen
Produktcode
DAC8560EVM
EVM Operation
www.ti.com
3.2
Host Processor Interface
The host processor basically drives the DAC; so, the DAC's proper operation depends on the successful
configuration between the host processor and the EVM board. In addition, a properly written code also is
required to operate the DAC.
configuration between the host processor and the EVM board. In addition, a properly written code also is
required to operate the DAC.
A custom cable can be made specific to the host interface platform. The EVM allows interface to the host
processor through J2 header connector for the serial control signals and the serial data input. The output
can be monitored through the J4 header connector.
processor through J2 header connector for the serial control signals and the serial data input. The output
can be monitored through the J4 header connector.
An interface adapter board also is available for a specific TI DSP starter kit as well as an MSP430-based
microprocessor as previously mentioned. Using the interface board alleviates the tedious task of building
customized cables and allows easy configuration of a simple evaluation system.
microprocessor as previously mentioned. Using the interface board alleviates the tedious task of building
customized cables and allows easy configuration of a simple evaluation system.
The DAC8560 interfaces with any host processor capable of handling SPI protocols or the popular TI
DSP. For more information regarding the DAC8560 data interface, see the DAC8560 data sheet
(
DSP. For more information regarding the DAC8560 data interface, see the DAC8560 data sheet
(
3.3
EVM Stacking
The stacking of EVMs is possible if the user needs to evaluate two DAC8560 devices to yield a total of up
to two (DAC8560) channel outputs. A maximum of two EVMs are allowed because the output terminal, J4,
dictates the number of DAC channels that can be connected without output bus contention.
to two (DAC8560) channel outputs. A maximum of two EVMs are allowed because the output terminal, J4,
dictates the number of DAC channels that can be connected without output bus contention.
shows
how the DAC output channels are mapped into the output terminal, J4, with respect to the jumper position
of W2 and W7.
of W2 and W7.
Table 2. DAC Output Channel Mapping
Jumper
Reference
Function
Position
1-2
DAC output (V
OUT
) is routed to J4-2.
W2
2-3
DAC output (V
OUT
) is routed to J4-6.
1-2
DAC sense pin (V
FB
) is routed to J4-10, if R1 jumper resistor is disconnected.
W7
2-3
DAC sense pin (V
FB
) is routed to J4-14, if R1 jumper resistor is disconnected.
In order to allow exclusive control of each EVM that is stacked together, the DAC8560 must have a
separate SYNC signal. This is accomplished in hardware by routing the SYNC signal of the first EVM
through CS (P2/J2 pin 1) by shorting pins 1-2 of jumper W6. The second EVM should use the FSX signal
(P2/J2 pin 7) to drive the SYNC signal by shorting pins 2-3 of the jumper W6. The output can be mapped
as described in
separate SYNC signal. This is accomplished in hardware by routing the SYNC signal of the first EVM
through CS (P2/J2 pin 1) by shorting pins 1-2 of jumper W6. The second EVM should use the FSX signal
(P2/J2 pin 7) to drive the SYNC signal by shorting pins 2-3 of the jumper W6. The output can be mapped
as described in
for each of the EVM stacked.
3.4
The Output Operational Amplifier
The EVM includes an optional signal-conditioning circuit for the DAC output through an external
operational amplifier, U2. During stacking of the EVMs, only one DAC output channel can be monitored at
any given time for evaluation because the odd-numbered pins (J4-1 to J4-7) are tied together. If both
outputs are needed to be buffered and monitored at the same time, the traces in the back of the EVM
board are exposed for ease of cutting. When cutting a trace, make sure to cut through the trace adjacent
to the appropriate J4 header pin and not at the curvy line. If the trace is cut through the curving line, the
signal may not propagate through to the operational amplifier. See
operational amplifier, U2. During stacking of the EVMs, only one DAC output channel can be monitored at
any given time for evaluation because the odd-numbered pins (J4-1 to J4-7) are tied together. If both
outputs are needed to be buffered and monitored at the same time, the traces in the back of the EVM
board are exposed for ease of cutting. When cutting a trace, make sure to cut through the trace adjacent
to the appropriate J4 header pin and not at the curvy line. If the trace is cut through the curving line, the
signal may not propagate through to the operational amplifier. See
and the schematic included in
this manual.
The output operational amplifier is set to unity gain configuration by default but can be modified by simple
jumper settings. Nevertheless, the raw output of the DAC can be probed through the specified pins of the
J4 output terminal, which also provides mechanical stability when stacking or plugging into any interface
board. In addition, it provides easy access for monitoring up to two (DAC8560) DAC channels when
stacking two EVMs together (see section 3.3).
jumper settings. Nevertheless, the raw output of the DAC can be probed through the specified pins of the
J4 output terminal, which also provides mechanical stability when stacking or plugging into any interface
board. In addition, it provides easy access for monitoring up to two (DAC8560) DAC channels when
stacking two EVMs together (see section 3.3).
The following sections describe the different configurations of the output amplifier, U2.
10
DAC8560 Evaluation Module
SLAU211A – March 2007 – Revised November 2009
Copyright © 2007–2009, Texas Instruments Incorporated