Texas Instruments LMK03806B Evaluation Board LMK03806BEVAL/NOPB LMK03806BEVAL/NOPB Datenbogen

 
 

 

 

4        SNAU075A 

LMK3806 Evaluation Board 

November 2013 

Copyright © 2013, Texas Instruments Incorporated

 

 

Figure 1: Quick Start Diagram ...................................................................................................................................... 6

 

Figure 2: Selecting a Default Mode for the LMK03806B Device .................................................................................. 7

 

Figure 4: Loading the Device ........................................................................................................................................ 9

 

Figure 5: Setting the Default mode for LMK03806 ....................................................................................................... 9

 

Figure 6: Setting Digital Delay, Clock Divider, Analog Delay, and Output Format for CLKout0 ................................. 10

 

Figure 7: Setting LVCMOS modes ............................................................................................................................. 10

 

Figure 8: Port Setup Tab ............................................................................................................................................. 16

 

Figure 9: Clock Outputs Tab ....................................................................................................................................... 17

 

Figure 10: PLL Tab ..................................................................................................................................................... 18

 

Figure 11: Bits/Pins Tab .............................................................................................................................................. 20

 

Figure 12: Registers Tab ............................................................................................................................................ 22

 

Figure 13: LMK03806B PLL VCO div2 LVPECL Phase Noise ................................................................................... 23

 

Figure 14: LMK03806B div8 CLKout LVPECL Phase Noise ...................................................................................... 25

 

Figure 15: LMK03806B div8 CLKout LVDS Phase Noise .......................................................................................... 25

 

Figure 16: LMK03806B div8 CLKout LVCMOS Phase Noise .................................................................................... 26

 

Figure 17 - LMK03806 Power Supply Schematic ....................................................................................................... 27

 

Figure 18 - LMK03806 Device Schematic .................................................................................................................. 28

 

Figure 19 - Outputs, (OSCout, CLKout0/1/2/3) Schematics ....................................................................................... 29

 

Figure 20 - LMK03806 Clock Outputs 4 through 7 Schematics ................................................................................. 30

 

Figure 21 - LMK03806 Clock Outputs 8 through 11 Schematics ............................................................................... 31

 

Figure 22: PCB Stackup ............................................................................................................................................. 35

 

Figure 23: Layer 1 - Top ............................................................................................................................................. 36

 

Figure 24: Layer 2 – RF Ground Plane ....................................................................................................................... 37

 

Figure 25: Layer 3 – Vcc Planes ................................................................................................................................. 38

 

Figure 26: Layer 4 - Bottom ........................................................................................................................................ 39

 

Figure 27: Top and Bottom (Composite) .................................................................................................................... 40

 

  

 

Table 1: EVM Contents ................................................................................................................................................. 5

 

Table 2: Default CodeLoader Modes for LMK03806 .................................................................................................... 7

 

Table 3: PLL Loop Filter Parameters for LMK03806B ................................................................................................ 11

 

Table 4: Evaluation Board Inputs and Outputs ........................................................................................................... 12

 

Table 5: Registers Controls and Descriptions in PLL Tab .......................................................................................... 18

 

Table 6: Datasheet to PCB Silkscreen Updates ......................................................................................................... 20

 

Table 7: Register Controls and Descriptions on Bits/Pins Tab ................................................................................... 21

 

Table 8: LMK03806B PLL VCO div2 Phase Noise and RMS Jitter (fs) ..................................................................... 23

 

Table 9: Typical Phase Noise Performance Plot Setup .............................................................................................. 24

 

Table 10: LMK03806B Phase Noise and RMS Jitter for Different CLKout Output Formats and Frequencies .......... 24

 

Table 11: Bill of Materials for LMK03806BEVAL Boards ............................................................................................ 32