Texas Instruments SN65LVDS125 Evaluation Module SN65LVDS125AEVM SN65LVDS125AEVM Datenbogen
Produktcode
SN65LVDS125AEVM
DE
V
OY
or V
OZ
V
OZ
or V
OY
3 V
1.5 V
0 V
0 V
1.4 V
1.25 V
1.2 V
1.25 V
1.2 V
1.2 V
1.15 V
1 V
1.15 V
1 V
t
PZH
t
PHZ
t
PZL
t
PLZ
Y
Z
1 pF
V
OY
V
OZ
49.9
Ω
±
1%
1.2 V
49.9
Ω
±
1%
1 V or 1.4 V
1.2 V
DE
Clock Input
0 V
V
A
V
B
1/fo
PRBS Input
0 V
V
A
V
B
PRBS Output
0 V
V
Y
V
Z
0 V
0 V
0 V
V
Y
- V
Z
V
Y
- V
Z
V
Y
- V
Z
Actual Output
Ideal Output
1/fo
Period Jitter
Cycle-to-Cycle Jitter
Peak-to-Peak Jitter
Actual Output
t
jit(pp)
t
c(n)
t
c(n)
t
c(n +1)
t
jit(pp)
= | t
c(n)
- 1/fo |
t
jit(cc)
= | t
c(n)
- t
c(n + 1)
|
SLLS595C
–
OCTOBER 2003
–
REVISED JUNE 2011
PARAMETER MEASUREMENT INFORMATION (continued)
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤
1 ns, pulse-repetition rate
(PRR) = 0.5 Mpps, pulse width = 500
±
10 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
NOTE: All input pulses are supplied by an Agilent 81250 Stimulus System. The measurement is made on a TEK TDS6604
running TDSJIT3 application software.
Figure 6. Driver Jitter Measurement Waveforms
8
Copyright
©
2003
–
2011, Texas Instruments Incorporated