Texas Instruments DDC11XEVM-PDK - DDC11xEVM-PDK Evaluation Module DDC11XEVM-PDK DDC11XEVM-PDK Datenbogen
Produktcode
DDC11XEVM-PDK
DDCMB Hardware Description
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The inputs to the DDC114 device can be provided individually on the J6–J9 (AIN1 to AIN4) BNC
connectors. For testing purposes, all four channels can be driven with the same signal if it is provided on
J5 (AINCOM). Each of the four input channels connect to a jumper (JP4–JP7) for selecting whether the
input is common (AINCOM), or if each input is individually connected through the BNC connectors
(J6–J9). Each jumper is connected to a 10M
connectors. For testing purposes, all four channels can be driven with the same signal if it is provided on
J5 (AINCOM). Each of the four input channels connect to a jumper (JP4–JP7) for selecting whether the
input is common (AINCOM), or if each input is individually connected through the BNC connectors
(J6–J9). Each jumper is connected to a 10M
Ω
resistor (R16–R19), which in turn goes to one of the input
channels (AIN1–AIN4). The default configuration is to have each jumper connect to J5 (AINCOM) so that
one signal feeds all four channels through an individual 10M
one signal feeds all four channels through an individual 10M
Ω
resistor per channel. Pin socket locations
are also provided at each BNC connector to allow a resistor or jumper to connect the BNC to the actual
input channel. Refer to the appended schematic for details. The factory setting is all pin sockets open.
input channel. Refer to the appended schematic for details. The factory setting is all pin sockets open.
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DDCMB Hardware Description
The PC interface board, or motherboard, is called the DDCMB. This board has a USB interface for
connecting to a PC; the USB interfaces to a small microcontroller that controls the functions of a Xilinx
Spartan™-3 FPGA. The FPGA generates all the timing signals that are sent to the DUT and handles
communication of data between the DUT and the PC.
connecting to a PC; the USB interfaces to a small microcontroller that controls the functions of a Xilinx
Spartan™-3 FPGA. The FPGA generates all the timing signals that are sent to the DUT and handles
communication of data between the DUT and the PC.
The DDCMB is designed to be extremely flexible and therefore has many configurable settings. These
settings are described in the following subsections. When using the board with this evaluation kit, the
default settings should be used. Refer to the appended schematic and the layout diagram in
settings are described in the following subsections. When using the board with this evaluation kit, the
default settings should be used. Refer to the appended schematic and the layout diagram in
.
6.1
Motherboard Connectors
The USB interface to a personal computer is provided on J1. The connection to a DUT daughtercard is
made using the J4 50-pin socket.
made using the J4 50-pin socket.
One connector is only provided for use in manufacturing the DDCMB. J2 is a JTAG header used for the
configuration of the FPGA and downloading firmware to the EEPROM.
configuration of the FPGA and downloading firmware to the EEPROM.
Power is supplied to the DDCMB in one of several ways. One way is directly through the screw terminal
block J3. This input should be +5VDC. Another way is through connector J5. This connector accepts a
6V–9V DC voltage from an ac/dc wall adapter supply. AC adapters must be tip-positive/sleeve-negative,
with an inner size of 2.5mm and outer size of 5.5mm. A third option is to power the board using the
voltage supplied from the USB connection. Jumper JP3 allows selection of the USB supply or one of the
two external supply options. The factory default settings for JP3 is the USB connection.
block J3. This input should be +5VDC. Another way is through connector J5. This connector accepts a
6V–9V DC voltage from an ac/dc wall adapter supply. AC adapters must be tip-positive/sleeve-negative,
with an inner size of 2.5mm and outer size of 5.5mm. A third option is to power the board using the
voltage supplied from the USB connection. Jumper JP3 allows selection of the USB supply or one of the
two external supply options. The factory default settings for JP3 is the USB connection.
6.2
Motherboard Jumpers
Refer to
for location of jumpers on the DDCMB.
6.2.1
Clock Options
Two clocks are used on the DDCMB: a clock for the USB microcontroller, and a clock for the FPGA. The
FPGA generates all clocking signals for the DUT daughtercards. The USB microprocessor uses a 24MHz
crystal (X1), while the FPGA (U7) uses an 80MHz crystal oscillator (U8).
FPGA generates all clocking signals for the DUT daughtercards. The USB microprocessor uses a 24MHz
crystal (X1), while the FPGA (U7) uses an 80MHz crystal oscillator (U8).
6.2.2
Power Supplies
JP1 provides 3.3V while JP2 provides 5V to the daughtercard via the 50-pin connector; if these options
are used, assure that the daughtercard is not also supplying 3.3V or 5V locally. The factory default setting
for JP1 and JP2 is installed.
are used, assure that the daughtercard is not also supplying 3.3V or 5V locally. The factory default setting
for JP1 and JP2 is installed.
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DDC11xEVM-PDK User's Guide
SLAU234A – October 2007 – Revised July 2010
Copyright © 2007–2010, Texas Instruments Incorporated