Texas Instruments TLV62080EVM-756 Evaluation Module TLV62080EVM-756 TLV62080EVM-756 Datenbogen
Produktcode
TLV62080EVM-756
VI
N
N
Exposed
Thermal PAD
Thermal PAD
VIA to Ground Plane
VIN
High-input
Bypass
Capacitor
Feedback
Resistor 1
Resistor 1
VIN
High-frequency
Bypass
Capacitor
Ground
SW
PG
VO
S
EN
G
N
D
G
N
D
F
B
Output
Inductor
Output
Capacitor 1
Capacitor 1
Feedback
Resistor 2
Resistor 2
Ground
Output
Capacitor 2
Capacitor 2
V
OUT
SW
PG Resistor
VIA to V
IN
or V
OUT
Plane
SLVSAK9E – OCTOBER 2011 – REVISED FEBRUARY 2014
10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 2.5 V (2.7 V for the TLV62084
device) and 5.5 V. This input supply must be well regulated. If the input supply is located more than a few inches
from the TLV6208x converter additional bulk capacitance may be required in addition to the ceramic bypass
capacitors. An electrolytic or tantalum capacitor with a value of 47
device) and 5.5 V. This input supply must be well regulated. If the input supply is located more than a few inches
from the TLV6208x converter additional bulk capacitance may be required in addition to the ceramic bypass
capacitors. An electrolytic or tantalum capacitor with a value of 47
μF is a typical choice.
11 Layout
11.1 Layout Guidelines
The PCB layout is an important step to maintain the high performance of the TLV62080 and TLV62084 devices.
•
•
Place input and output capacitors, along with the inductor, as close as possible to the IC which keeps the
traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance.
traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance.
•
Use a common-power GND.
•
Properly connect the low side of the input and output capacitors to the power GND to avoid a GND potential
shift.
shift.
•
The sense traces connected to FB and VOS terminals are signal traces. Keep these traces away from SW
nodes.
nodes.
•
Use care to avoid noise induction. By a direct routing, parasitic inductance can be kept small.
•
Use GND layers for shielding if needed.
11.2 Layout Example
Figure 18. PCB Layout Suggestion
16
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