Texas Instruments THS3111 Evaluation Module THS3111EVM THS3111EVM Datenbogen
Produktcode
THS3111EVM
1
2
3
4
8
7
6
5
NC
V
IN −
V
IN +
V
S−
NC
V
S+
V
OUT
NC
NC = No Internal Connection
NOTE: The device with the power-down option defaults to the ON state if no signal is applied to the PD pin. Additionally, the REF pin
functional range is from V
functional range is from V
to (V
4 V).
S
S+
-
-
1
2
3
4
8
7
6
5
REF
V
IN−
V
IN+
V
S−
V
S+
V
OUT
NC
NC = No Internal Connection
PD
THS3110
THS3111
D, DGN
TOP VIEW
D, DGN
TOP VIEW
SLOS422E – SEPTEMBER 2003 – REVISED OCTOBER 2009
........................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS
(1)
PACKAGED DEVICE
T
A
PLASTIC SMALL OUTLINE SOIC (D)
PLASTIC MSOP (DGN)
(2)
SYMBOL
THS3110CD
THS3110CDGN
0°C to +70°C
BJB
THS3110CDR
THS3110CDGNR
THS3110ID
THS3110IDGN
–40°C to +85°C
BIR
THS3110IDR
THS3110IDGNR
THS3111CD
THS3111CDGN
0°C to +70°C
BJA
THS3111CDR
THS3111CDGNR
THS3111ID
THS3111IDGN
–40°C to +85°C
BIS
THS3111IDR
THS3111IDGNR
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at
web site at
(2)
The PowerPAD is electrically isolated from all other pins.
DISSIPATION RATINGS TABLE
POWER RATING
T
J
= +125°C
PACKAGE
θ
JC
(°C/W)
θ
JA
(°C/W)
T
A
= +25°C
T
A
= +85°C
D-8
(1)
38.3
95
1.05 W
421 mW
DGN-8
(2)
4.7
58.4
1.71 W
685 mW
(1)
These data were taken using the JEDEC standard low-K test PCB. For the JEDEC proposed high-K test PCB, the
θ
JA
is 95°C/W with
power rating at T
A
= +25°C of 1.05 W.
(2)
These data were taken using 2 oz. trace and copper pad that is soldered directly to a 3 inch × 3 inch (76,2 mm × 76,2 mm) PCB. For
further information, refer to the
further information, refer to the
section of this data sheet.
2
Copyright © 2003–2009, Texas Instruments Incorporated
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