Texas Instruments LM96080 Evaluation Board LM96080EB/NOPB LM96080EB/NOPB Datenbogen
Produktcode
LM96080EB/NOPB
SNAS465D – SEPTEMBER 2009 – REVISED MARCH 2013
Using the Configuration Register
The Configuration Register (address 00h) provides control for the LM96080. At power on, the ADC is stopped
and INT_Clear (bit 3) is asserted, clearing the INT and RST_OUT/OS hardwire outputs. The Configuration
Register starts and stops the LM96080, enables and disables INT outputs, clears and sets GPI (CI) and GPO I/O
pins, initiates reset pulse on RST_OUT/OS pin, and provides the reset function described in the
and INT_Clear (bit 3) is asserted, clearing the INT and RST_OUT/OS hardwire outputs. The Configuration
Register starts and stops the LM96080, enables and disables INT outputs, clears and sets GPI (CI) and GPO I/O
pins, initiates reset pulse on RST_OUT/OS pin, and provides the reset function described in the
section.
Bit 0 of the Configuration Register, START, controls the monitoring loop of the LM96080. Setting bit 0 low stops
the LM96080 monitoring loop and puts the LM96080 in shutdown mode, reducing power consumption. Serial Bus
communication is possible with any register in the LM96080 although activity on these lines will increase
consumption current. Taking bit 0 high starts the monitoring loop, described in more detail subsequently.
the LM96080 monitoring loop and puts the LM96080 in shutdown mode, reducing power consumption. Serial Bus
communication is possible with any register in the LM96080 although activity on these lines will increase
consumption current. Taking bit 0 high starts the monitoring loop, described in more detail subsequently.
Bit 1 of the Configuration Register, INT Enable, enables the INT Interrupt hardwire output when this bit is taken
high.
high.
Bit 2 of the Configuration Register, INT Polarity Select, defines whether the INT pin is NMOS or PMOS open
drain.
drain.
Bit 3, INT_Clear, clears the INT output when taken high. The LM96080 monitoring function will stop until bit 3 is
taken low. The content of the Interrupt Status Registers (addresses 01h - 02h) will not be affected.
taken low. The content of the Interrupt Status Registers (addresses 01h - 02h) will not be affected.
Bit 4, RESET, when taken high, will initiate a 10 ms RESET signal on the RST_OUT/OS output when OS Pin
Enable (address 05h, bit 6) = 0 and RST Enable (address 05h, bit 7) = 1.
Enable (address 05h, bit 6) = 0 and RST Enable (address 05h, bit 7) = 1.
When bit 5, Chassis Clear, is taken high, the GPI (Chassis Intrusion) pin is driven low for 10 ms.
Bit 6 of the configuration register, GPO, sets or clears the GPO output. This pin can be used in software power
control by activating an external power control MOSFET.
control by activating an external power control MOSFET.
Starting Conversions
Start the monitoring function (Analog inputs, temperature, and fan speeds) in the LM96080 by writing to the
Configuration Register and setting INT_Clear (bit 3) low and Start (bit 0) high. The LM96080 then performs a
round-robin monitoring of all analog inputs, temperature, and fan speed inputs. The sequence of items being
monitored corresponds to locations in the Value RAM (except for the Temperature reading) as follows:
Configuration Register and setting INT_Clear (bit 3) low and Start (bit 0) high. The LM96080 then performs a
round-robin monitoring of all analog inputs, temperature, and fan speed inputs. The sequence of items being
monitored corresponds to locations in the Value RAM (except for the Temperature reading) as follows:
1. Temperature
2. IN0
3. IN1
4. IN2
5. IN3
6. IN4
7. IN5
8. IN6
9. Fan 1
10. Fan 2
Reading Conversion Results
The conversion results are available in the Value RAM (addresses 20h - 29h). Conversions can be read at any
time and will provide the result of the last conversion. If a conversion is in progress while a communication is
started, that conversion will be completed, and the internal register(s) will not be updated until the communication
is complete.
time and will provide the result of the last conversion. If a conversion is in progress while a communication is
started, that conversion will be completed, and the internal register(s) will not be updated until the communication
is complete.
A typical sequence of events upon power on of the LM96080 would consist of:
1. Set WATCHDOG Limits
2. Set Interrupt Masks
3. Start the LM96080 monitoring process
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