Texas Instruments Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.5 GHz VCO LMK04806BEVAL/NOPB LMK04806BEVAL/NOPB Datenbogen
Produktcode
LMK04806BEVAL/NOPB
L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
22
Programming 0-Delay Mode in CodeLoader
Overview
When enabling the 0-Delay mode the feedback path of the VCO is altered to include a clock
output. See the datasheet for more details on 0-Delay functionality.
The current version of the CodeLoader software does not include this extra divider in the
frequency calculations when in holdover mode. To successfully lock the LMK04800 device in a
0-Delay mode the user must program the device “manually” account for this divider.
Programming “manually” means that the VCO frequency and therefore the clock output
frequencies displayed by the CodeLoader software may be incorrect. For the LMK04800 device
to lock properly the divider values must be programmed correctly. The frequencies displayed in
the application are only for the benefit of the user and for proper automatic programming of the
OSCin_FREQ register which will not be affected by 0-Delay.
When using the device in Dual Loop mode vs. Single Loop mode different procedures are used
to cause the device to lock when using the CodeLoader software. The following two sections
describe the process for when the LMK04800 device is programmed for a Dual Loop mode and
Single Loop mode respectively. Each section contains a brief introduction, the programming
steps to execute to make the device lock, and finally a detailed section discussing the
workaround and some example cases.
output. See the datasheet for more details on 0-Delay functionality.
The current version of the CodeLoader software does not include this extra divider in the
frequency calculations when in holdover mode. To successfully lock the LMK04800 device in a
0-Delay mode the user must program the device “manually” account for this divider.
Programming “manually” means that the VCO frequency and therefore the clock output
frequencies displayed by the CodeLoader software may be incorrect. For the LMK04800 device
to lock properly the divider values must be programmed correctly. The frequencies displayed in
the application are only for the benefit of the user and for proper automatic programming of the
OSCin_FREQ register which will not be affected by 0-Delay.
When using the device in Dual Loop mode vs. Single Loop mode different procedures are used
to cause the device to lock when using the CodeLoader software. The following two sections
describe the process for when the LMK04800 device is programmed for a Dual Loop mode and
Single Loop mode respectively. Each section contains a brief introduction, the programming
steps to execute to make the device lock, and finally a detailed section discussing the
workaround and some example cases.
Dual Loop 0-Delay Mode Examples
In Dual Loop 0-Delay Modes, MODE = 2 or MODE = 5, the feedback from the VCXO of PLL1
to the PLL1 N divider is broken and a clock output will drive the PLL1 N divider. This permits
phase alignment between the clock output and the clock input (0-Delay). As such, the PLL1_N
and PLL1_R divide values may need to be adjusted to permit the LMK04800 to lock.
to the PLL1 N divider is broken and a clock output will drive the PLL1 N divider. This permits
phase alignment between the clock output and the clock input (0-Delay). As such, the PLL1_N
and PLL1_R divide values may need to be adjusted to permit the LMK04800 to lock.
Programming Steps
1. Program a Dual Loop 0-Delay mode.
2. Enable the feedback mux. EN_FEEDBACK_MUX = 1.
3. Select clock output for feedback with the feedback mux. FEEDBACK_MUX = User
2. Enable the feedback mux. EN_FEEDBACK_MUX = 1.
3. Select clock output for feedback with the feedback mux. FEEDBACK_MUX = User
value.
4. Program the VCXO (VCO) frequency of PLL1 tab to the clock output frequency selected
by the feedback mux.
If for any reason the CLKout frequency is less than the phase detector frequency, the PLL1 R
divider must be increased so that the phase detector is at the same or lower value than the
CLKout frequency.
Details
When using the CodeLoader software in Dual Loop 0-Delay mode, programming the VCXO
(VCO) frequency of the PLL1 tab to the frequency of the fed back output clock will re-program
the PLL1 N divider to allow the LMK04800 will be able to lock. The PLL1 loop has been
altered and actual VCXO no longer directly feeds into PLL1 N divider. The VCXO is only used
(VCO) frequency of the PLL1 tab to the frequency of the fed back output clock will re-program
the PLL1 N divider to allow the LMK04800 will be able to lock. The PLL1 loop has been
altered and actual VCXO no longer directly feeds into PLL1 N divider. The VCXO is only used