Texas Instruments DAC34H84EVM - DAC34H84 Evaluation Module DAC34H84EVM DAC34H84EVM Datenbogen

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DAC34H84EVM

Software Control

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OSTR: sync from the external LVPECL OSTR signal. Clock divider sync must be enabled with
OSTR set as sync source.

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SYNC: sync from the external LVDS SYNC signal.

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SIF SYNC: sync from SIF Sync. Uncheck and check the SIF Sync button for sync event.

•

NCO: allows fine mixing of the I/Q signal. The procedure to adjust the NCO mixing frequency are listed
below:

1. Enter the DAC sampling frequency in Fsample.

2. Enter the desired mixing frequency in both NCO freq_AB and NCO freq_CD.

3. Press Update freq

4. Sync the NCO block from the following options:

•

REGWR: auto-sync from SIF register write. Writing to either Phase OffsetAB or Phase
OffsetCD can create a sync event.

•

OSTR: sync from the external LVPECL OSTR signal. Clock divider sync must be enabled with
OSTR set as sync source. Refer to the datasheet for OSTR period requirement.

•

SYNC: sync from the external SYNC signal

•

SIF SYNC: sync from SIF Sync. Uncheck and check the SIF Sync button for sync event.

2.2.3

Output Control Options

Figure 5. Output control Options

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Output Options: allows the configuration of reference, output polarity, and output delay

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Data Routing: provides flexible routing of the A, B, C, and D digital path to the desired output channels.
Note: The DAC3482 does not support this mode.

•

DAC Gain: configures the full-scale DAC current and DAC3484/DAC3482 mode. With Rbiaj resistor set
at 1.28k

–

DAC Gain = 15 for 30mA full-scale current.

–

DAC Gain = 10 for 20mA full-scale current (default).

•

Output Shutoff On: allows outputs to shut-off when DACCLK GONE, DATACLK GONE, or FIFO
COLLISION alarm event occurs.

DAC348x EVM

SLAU432 – February 2012

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