Texas Instruments LM5069EVAL Evaluation Board LM5069EVAL/NOPB LM5069EVAL/NOPB Datenbogen
Produktcode
LM5069EVAL/NOPB
Theory of Operation
3
Theory of Operation
The LM5069 provides intelligent control of the power supply connections of a load which is to be
connected to a live power source. The two primary functions of a hot swap circuit are in-rush current
limiting during turn-on, and monitoring of the load current for faults during normal operation. Additional
functions include Under-Voltage Lock-Out (UVLO) and Over-Voltage Lock-Out (OVLO) to ensure voltage
is supplied to the load only when the system input voltage is within a defined range, power limiting in the
series pass FET (Q1) during turn-on, and a Power Good logic output (PGD) to indicate the circuit status.
connected to a live power source. The two primary functions of a hot swap circuit are in-rush current
limiting during turn-on, and monitoring of the load current for faults during normal operation. Additional
functions include Under-Voltage Lock-Out (UVLO) and Over-Voltage Lock-Out (OVLO) to ensure voltage
is supplied to the load only when the system input voltage is within a defined range, power limiting in the
series pass FET (Q1) during turn-on, and a Power Good logic output (PGD) to indicate the circuit status.
Upon applying the input voltage to the LM5069 (for example, SW1 is switched on), Q1 is initially held off
for the insertion delay (
for the insertion delay (
≊
600 ms) to allow ringing and transients at the input to subside. At the end of the
insertion delay, if the input voltage at VIN is between the UVLO and OVLO thresholds, Q1 is turned on in
a controlled manner to limit the in-rush current. If the in-rush current were not limited during turn-on, the
current would be high (very high!) as the load capacitors (C3, C4) charge up, limited only by the surge
current capability of the voltage source, C7’s characteristics, and the wiring resistance (a few milliohms).
That very high current could damage the edge connector, PC board traces, and possibly the load
capacitors receiving the high current. Additionally, the dV/dt at the load’s input is controlled to reduce
possible EMI problems.
a controlled manner to limit the in-rush current. If the in-rush current were not limited during turn-on, the
current would be high (very high!) as the load capacitors (C3, C4) charge up, limited only by the surge
current capability of the voltage source, C7’s characteristics, and the wiring resistance (a few milliohms).
That very high current could damage the edge connector, PC board traces, and possibly the load
capacitors receiving the high current. Additionally, the dV/dt at the load’s input is controlled to reduce
possible EMI problems.
The LM5069 limits in-rush current to a safe level using a two step process. In the first portion of the turn-
on cycle, when the voltage differential across Q1 is highest, Q1’s power dissipation is limited to a peak of
45W by monitoring its drain current (the voltage across R10) and its drain-to-source voltage. Their product
is maintained constant by controlling the drain current as the drain-to-source voltage decreases (as the
output voltage increases). This is shown in the constant power portion of
on cycle, when the voltage differential across Q1 is highest, Q1’s power dissipation is limited to a peak of
45W by monitoring its drain current (the voltage across R10) and its drain-to-source voltage. Their product
is maintained constant by controlling the drain current as the drain-to-source voltage decreases (as the
output voltage increases). This is shown in the constant power portion of
where the drain current
is increasing to I
LIM
. When the drain currrent reaches the current limit threshold (5.5 Amps), it is then
maintained constant as the output voltage continues to increase. When the output voltage reaches the
input voltage (V
input voltage (V
DS
decreases to near zero), the drain current then reduces to a value determined by the
load. Q1’s gate-to-source voltage then increases to
≊
12V above the OUT voltage. The circuit is now in
normal operation mode.
Monitoring of the load current for faults during normal operation is accomplished using the current limit
circuit described above. If the load current increases to 5.5 Amps (55 mV across R10), Q1’s gate is
controlled to prevent the current from increasing further. When current limiting takes effect, the fault timer
limits the duration of the fault. At the end of the fault timeout period (
circuit described above. If the load current increases to 5.5 Amps (55 mV across R10), Q1’s gate is
controlled to prevent the current from increasing further. When current limiting takes effect, the fault timer
limits the duration of the fault. At the end of the fault timeout period (
≊
38 ms) Q1 is shut off, denying
current to the load. The LM5069-2 then initiates a restart every 7.7 seconds. The restart consists of
turning on Q1 and monitoring the load current to determine if the fault is still present. After the fault is
removed, the circuit powers up to normal operation at the next restart.
turning on Q1 and monitoring the load current to determine if the fault is still present. After the fault is
removed, the circuit powers up to normal operation at the next restart.
In a sudden overload condition (the output is shorted to ground), it is possible the current could increase
faster than the response time of the current limit circuit. In this case, the circuit breaker sensor shuts off
Q1’s gate rapidly when the voltage across R10 reaches
faster than the response time of the current limit circuit. In this case, the circuit breaker sensor shuts off
Q1’s gate rapidly when the voltage across R10 reaches
≊
105 mV. When the current reduces to the
current limit threshold, the current limit circuitry then takes over.
The PGD logic level output is low during turn-on, and switches high when the output voltage at OUT has
increased to within 1.25V of the input voltage, signifying the turn-on procedure is essentially complete. If
the OUT voltage decreases more than 2.5V below VIN due to a fault, PGD switches low. The high level
voltage at PGD can be any appropriate voltage up to +80V, and can be higher or lower than the voltages
at VIN and OUT.
increased to within 1.25V of the input voltage, signifying the turn-on procedure is essentially complete. If
the OUT voltage decreases more than 2.5V below VIN due to a fault, PGD switches low. The high level
voltage at PGD can be any appropriate voltage up to +80V, and can be higher or lower than the voltages
at VIN and OUT.
The UVLO and OVLO thresholds are set by resistors R1-R3. The UVLO and OVLO thresholds are
reached when the voltage at the UVLO and OVLO pins each reach 2.5V, respectively. The internal 21µA
current sources provide hysteresis for each of the thresholds.
reached when the voltage at the UVLO and OVLO pins each reach 2.5V, respectively. The internal 21µA
current sources provide hysteresis for each of the thresholds.
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SNVA184B – September 2006 – Revised May 2013
AN-1522 LM5069 Evaluation Board
Copyright © 2006–2013, Texas Instruments Incorporated