Texas Instruments TMS320C6472 Evaluation Module TMDSEVM6472LE TMDSEVM6472LE Datenbogen
Produktcode
TMDSEVM6472LE
PRODUCTPREVIEW
SPRS612G
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JUNE 2009
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REVISED JULY 2011
7.8.3.8
PLL1 PLLDIV Ratio Change Status Register (DCHANGE)
Whenever a different ratio is written to the PLLDIV10 register, the PLLCTRL flags the change in the
PLLDIV ratio change status register (DCHANGE). During the GO operation, the PLL controller will only
change the divide ratio of the SYSCLK with the bit set in DCHANGE. Note that changed clocks will be
automatically aligned to other clocks if the corresponding ALN bit is set. The PLLDIV divider ratio change
status register is shown in
PLLDIV ratio change status register (DCHANGE). During the GO operation, the PLL controller will only
change the divide ratio of the SYSCLK with the bit set in DCHANGE. Note that changed clocks will be
automatically aligned to other clocks if the corresponding ALN bit is set. The PLLDIV divider ratio change
status register is shown in
and described in
31
16
Reserved
R-0
15
10
9
8
0
Reserved
SYSCLK10
Reserved
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-21. PLLDIV Divider Ratio Change Status Register (DCHANGE)
Table 7-27. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
Field
Value
Description
31:10
Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to these fields has no
effect.
effect.
9
SYSCLK10
Identifies when the SYSCLK10 divide ratio has been modified.
0
SYSCLK10 ratio has not been modified. When GOSET is set, SYSCLK10 will not be affected.
1
SYSCLK10 ratio has been modified. When GOSET is set, SYSCLK10 will change to the new ratio.
8:0
Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to these fields has no
effect.
effect.
158
C64x+ Peripheral Information and Electrical Specifications
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2009
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2011, Texas Instruments Incorporated
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