Texas Instruments TMS320C6472 Evaluation Module TMDSEVM6472LE TMDSEVM6472LE Datenbogen
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TMDSEVM6472LE
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ts127-2
ts127-0
ts127-1
ts000-7
ts000-6
ts000-1
ts000-3
ts000-5
ts000-4
ts000-2
ts000-0
6
5
1
3
2
CLKA/B
FSA/B
TRn
(A)
TXn
(A)
7
8
9
10
ts127-2
ts000-3
ts000-7
ts127-1
ts127-0
ts000-5
ts000-6
ts000-4
ts000-0
ts000-2
ts000-1
SPRS612G
–
JUNE 2009
–
REVISED JULY 2011
7.14.4 TSIP Electrical Data/Timing
Table 7-98. Timing Requirements for TSIP 2X Mode
(1)
(see
500/625/700
NO.
UNIT
MIN
MAX
1
t
c(CLK)
Cycle time, CLK rising edge to next CLK rising edge
61
(2)
ns
2
t
w(CLKL)
Pulse duration, CLK low
0.4 t
c(clk)
ns
3
t
w(CLKH)
Pulse duration, CLK high
0.4 t
c(clk)
ns
4
t
t(CLK)
Transition time, CLK high to low or CLK low to high
2
ns
5
t
su(FS-CLK)
Setup time, f
s
valid before rising CLK
5
ns
6
t
h(CLK-FS)
Hold time, f
s
valid after rising CLK
5
ns
7
t
su(TR-CLK)
Setup time, t
r
valid before rising CLK
5
ns
8
t
h(CLK-TR)
Hold time, t
r
valid before rising CLK
5
ns
9
t
d(CLKL-TX)
Delay time, CLK low to TX valid
1
12
ns
10
t
dis(CLKH-TXZ)
Disable time, CLK low to TX tristate
2
10
ns
(1)
Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 1b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 0. If the polarity
of any of the signals is inverted, then the timing references of that signal are also inverted.
of any of the signals is inverted, then the timing references of that signal are also inverted.
(2)
Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 30.5 ns and 15.2 ns, respectively.
A.
Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through
255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and
frame sync signals would require a RCVDATD=1 and a XMTDATD=1.
255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and
frame sync signals would require a RCVDATD=1 and a XMTDATD=1.
Figure 7-45. TSIP 2x Timing Diagram
214
C64x+ Peripheral Information and Electrical Specifications
Copyright
©
2009
–
2011, Texas Instruments Incorporated
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