Texas Instruments TMS320C6472 Evaluation Module TMDSEVM6472LE TMDSEVM6472LE Datenbogen
Produktcode
TMDSEVM6472LE
PRODUCTPREVIEW
SPRS612G
–
JUNE 2009
–
REVISED JULY 2011
4.3
Priority Allocation
On the C6472 device, DMA data transfers use a priority-based arbitration. The C64x+ megamodule,
EDMA, TSIP, and SRIO peripherals define their own priorities. The Ethernet and HPI peripherals do not
define their own priorities, while the UTOPIA-PDMA only partially defines its own priority. Priorities for
Ethernet, HPI, and UTOPIA-PDMA transfers should be assigned via the Priority Allocation (PRI_ALLOC)
register (see
EDMA, TSIP, and SRIO peripherals define their own priorities. The Ethernet and HPI peripherals do not
define their own priorities, while the UTOPIA-PDMA only partially defines its own priority. Priorities for
Ethernet, HPI, and UTOPIA-PDMA transfers should be assigned via the Priority Allocation (PRI_ALLOC)
register (see
). A value of 000b has the highest priority, while 111b has the lowest priority. (For
more information on the default priority values in the C64x+ megamodule, EDMA, TSIP, and SRIO
peripheral registers, see the device-compatible reference guides). TI recommends that these priority
registers be reprogrammed upon initial use.
peripheral registers, see the device-compatible reference guides). TI recommends that these priority
registers be reprogrammed upon initial use.
31
16
Reserved
R-1111 1111 1111 1111
15
14
12
11
8
UTOPIA-
EMAC1
Reserved
PDMA
(A)
R/W-1
R/W-111
R-1111
7
6
5
3
2
0
Reserved
HPI
EMAC0
R-11
R/W-111
R/W-111
LEGEND: R/W = Read/Write; R = Read only; -n = value at reset
A. UTOPIA-PDMA has 2 bits of priority in the module. The PRI_ALLOC register supplies only the middle significant bit of the priority for
this module.
this module.
Figure 4-2. Priority Allocation Register (PRI_ALLOC)
4.4
Configuration Switch Fabric
shows the connection between the C64x+ megamodule and the configuration switched central
resource (SCR). The configuration SCR is mainly used by the C64x+ megamodules to access peripheral
registers. The data SCR also has a connection to the configuration SCR which allows masters to access
most peripheral registers. The only registers not accessible by the data SCR through the configuration
SCR are the C64x+ megamodule configuration registers; these can only be accessed by the C64x+
megamodules.
registers. The data SCR also has a connection to the configuration SCR which allows masters to access
most peripheral registers. The only registers not accessible by the data SCR through the configuration
SCR are the C64x+ megamodule configuration registers; these can only be accessed by the C64x+
megamodules.
The configuration SCR uses 32-bit configuration buses running at a frequency equal to the CPU frequency
divided by 3.
divided by 3.
94
System Interconnect
Copyright
©
2009
–
2011, Texas Instruments Incorporated
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