Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 Datenbogen
Produktcode
TMDSADAP180TO100
V
V
(3.3 V)
DDIO
DDA
,
V
DD12
, V
DD18
t
w(RSL1)
t
h(boot-mode)
(C)
X1/X2
XRS
(D)
Boot-Mode
Pins
XCLKOUT
I/O Pins
User-code dependent
User-code dependent
Boot-ROM execution starts
Peripheral/GPIO function
Based on boot code
Based on boot code
GPIO pins as input
GPIO pins as input (state depends on internal PU/PD)
t
OSCST
User-code dependent
Address/Data/
Control
(Internal)
Address/data valid, internal boot-ROM code execution phase
User-code execution phase
t
d(EX)
(A)
(B)
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
6.5
Power Sequencing
There is no power sequencing requirement needed to ensure the device is in the proper state after reset
or to prevent the I/Os from glitching during power up and power down. (All I/Os, except for GPIO199, are
glitch-free during power up and power down.) No voltage larger than a diode drop (0.7 V) above V
or to prevent the I/Os from glitching during power up and power down. (All I/Os, except for GPIO199, are
glitch-free during power up and power down.) No voltage larger than a diode drop (0.7 V) above V
DDIO
should be applied to any digital pin (for analog pins, this value is 0.7 V above V
DDA
) prior to powering up
the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended
ways and produce unpredictable results.
ways and produce unpredictable results.
A.
Upon power up, PLLSYSCLK is OSCCLK/8. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, PLLSYSCLK is further divided by 4 before PLLSYSCLK appears at XCLKOUT. XCLKOUT = OSCCLK/32
during this phase.
state of 0, PLLSYSCLK is further divided by 4 before PLLSYSCLK appears at XCLKOUT. XCLKOUT = OSCCLK/32
during this phase.
B.
Boot ROM configures the SYSDIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that
XCLKOUT will not be visible at the pin until explicitly configured by user code.
XCLKOUT will not be visible at the pin until explicitly configured by user code.
C.
After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will
be based on user environment and could be with or without PLL enabled.
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will
be based on user environment and could be with or without PLL enabled.
D.
Using the XRS pin is optional due to the on-chip POR circuitry.
Figure 6-2. Power-On Reset
Copyright © 2012–2014, Texas Instruments Incorporated
Electrical Specifications
135
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