Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 Datenbogen
Produktcode
TMDSADAP180TO100
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
7.1.4
External Peripheral Interface
The EPI provides a high-speed parallel bus for interfacing external peripherals and memory. EPI is
accessible from both the Master Subsystem and the Control Subsystem. EPI has several modes of
operation to enable glueless connectivity to most types of external devices. Some EPI modes of operation
conform to standard microprocessor address/data bus protocols, while others are tailored to support a
variety of fast custom interfaces, such as those communicating with field-programmable gate arrays
(FPGAs) and complex programmable logic devices (CPLDs).
accessible from both the Master Subsystem and the Control Subsystem. EPI has several modes of
operation to enable glueless connectivity to most types of external devices. Some EPI modes of operation
conform to standard microprocessor address/data bus protocols, while others are tailored to support a
variety of fast custom interfaces, such as those communicating with field-programmable gate arrays
(FPGAs) and complex programmable logic devices (CPLDs).
The EPI peripheral can be accessed by the Cortex-M3 CPU, the Cortex-M3 DMA, the C28x CPU, and the
C28x DMA over the high-performance AHB bus. The Cortex-M3 CPU and the µDMA drive AHB bus
cycles directly through the Cortex-M3 Bus Matrix. The C28x CPU and DMA also connect to the Cortex-M3
Bus Matrix, but not directly. Before entering the Cortex-M3 Bus Matrix, the native C28x CPU and DMA bus
cycles are first converted to AHB protocol inside the MEM32-to-AHB Bus Bridge. After that, they pass
through the Frequency Gasket to reduce the bus frequency by a factor of 2 or 4. Inside the Cortex-M3 Bus
Matrix, the Cortex-M3 bus cycles may have to compete with C28x bus cycles for access to the AHB bus
on the way to the EPI peripheral. See
C28x DMA over the high-performance AHB bus. The Cortex-M3 CPU and the µDMA drive AHB bus
cycles directly through the Cortex-M3 Bus Matrix. The C28x CPU and DMA also connect to the Cortex-M3
Bus Matrix, but not directly. Before entering the Cortex-M3 Bus Matrix, the native C28x CPU and DMA bus
cycles are first converted to AHB protocol inside the MEM32-to-AHB Bus Bridge. After that, they pass
through the Frequency Gasket to reduce the bus frequency by a factor of 2 or 4. Inside the Cortex-M3 Bus
Matrix, the Cortex-M3 bus cycles may have to compete with C28x bus cycles for access to the AHB bus
on the way to the EPI peripheral. See
to see how EPI interfaces to the Concerto Master
Subsystem, the Concerto Control Subsystem, Resets, Clocks, and Interrupts.
NOTE
The Control Subsystem has no direct access to EPI in silicon revision 0 devices.
Depending on how the Real-Time Window registers are configured inside the Bus Matrix, the arbitration
between the Cortex-M3 and C28x bus cycles is fixed-priority with Cortex-M3 having higher priority than
C28x, or the C28x having the option to own the Bus Matrix for a fixed period of time (window)—effectively
stalling all Cortex-M3 accesses during that time. Another EPI register inside the Cortex-M3 Bus Matrix is
the Memory Protection Register, which enables assignments of chip-select spaces to Cortex-M3 or C28x
EPI accesses (or both). The assignments of chip-select spaces prevent a bus cycle (from any processor)
that does not own a given chip-select space, from getting through to EPI. The Real-time Window registers
are the only EPI-related registers that are configurable by the C28x. The Memory Protection Register is
configurable only by the Cortex-M3 CPU, as are all configuration registers inside the EPI peripheral.
between the Cortex-M3 and C28x bus cycles is fixed-priority with Cortex-M3 having higher priority than
C28x, or the C28x having the option to own the Bus Matrix for a fixed period of time (window)—effectively
stalling all Cortex-M3 accesses during that time. Another EPI register inside the Cortex-M3 Bus Matrix is
the Memory Protection Register, which enables assignments of chip-select spaces to Cortex-M3 or C28x
EPI accesses (or both). The assignments of chip-select spaces prevent a bus cycle (from any processor)
that does not own a given chip-select space, from getting through to EPI. The Real-time Window registers
are the only EPI-related registers that are configurable by the C28x. The Memory Protection Register is
configurable only by the Cortex-M3 CPU, as are all configuration registers inside the EPI peripheral.
shows the EPI registers and how they relate to individual blocks within the EPI.
Once a bus cycle arrives at the AHB bus interface inside the EPI peripheral, the bus cycle is routed to the
General-Purpose Block, SDRAM Block, or the Host Bus Module, depending on the operating mode
chosen through the EPI Configuration Register. Write cycles are buffered in a 4-word-deep Write FIFO;
therefore, in most cases, the write cycles do not stall the CPU or DMA unless the Write FIFO becomes
full. Read cycles can be handled in two different ways: blocking read cycles and non-blocking read cycles.
Blocking read cycles are implemented when the content of a Read Data Register is 0. Blocking reads stall
the CPU or DMA until the bus transaction completes. Non-blocking read cycles are triggered when a non-
zero value is written into a Read Data Register. A non-zero value being written into a Read Data register
triggers EPI to autonomously perform multiple data reads in the background (without involving CPU or
DMA) according to values stored inside the Read Address Register and the Read Size Register. The
incoming data is then temporarily stored in the Non-Blocking Read (NBR) FIFO until an EPI interrupt is
generated to prompt the CPU or DMA to read the FIFO without risk of stalling. Furthermore, EPI has
actually two sets of Data/Address/Size registers (set 0 and set 1) to enable ping-pong operation of non-
blocking reads. In a ping-pong operation, while the previously fetched data is being read by the CPU or
DMA from one end of the NBR FIFO, the next set of data words is simultaneously being deposited into the
other end of the NBR FIFO.
General-Purpose Block, SDRAM Block, or the Host Bus Module, depending on the operating mode
chosen through the EPI Configuration Register. Write cycles are buffered in a 4-word-deep Write FIFO;
therefore, in most cases, the write cycles do not stall the CPU or DMA unless the Write FIFO becomes
full. Read cycles can be handled in two different ways: blocking read cycles and non-blocking read cycles.
Blocking read cycles are implemented when the content of a Read Data Register is 0. Blocking reads stall
the CPU or DMA until the bus transaction completes. Non-blocking read cycles are triggered when a non-
zero value is written into a Read Data Register. A non-zero value being written into a Read Data register
triggers EPI to autonomously perform multiple data reads in the background (without involving CPU or
DMA) according to values stored inside the Read Address Register and the Read Size Register. The
incoming data is then temporarily stored in the Non-Blocking Read (NBR) FIFO until an EPI interrupt is
generated to prompt the CPU or DMA to read the FIFO without risk of stalling. Furthermore, EPI has
actually two sets of Data/Address/Size registers (set 0 and set 1) to enable ping-pong operation of non-
blocking reads. In a ping-pong operation, while the previously fetched data is being read by the CPU or
DMA from one end of the NBR FIFO, the next set of data words is simultaneously being deposited into the
other end of the NBR FIFO.
Copyright © 2012–2014, Texas Instruments Incorporated
Peripheral Information and Timings
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