Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 Datenbogen
Produktcode
TMDSADAP180TO100
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
Table 3-11. Master Subsystem RAMs (continued)
µDMA
M Address
Size
C Address
Master Subsystem RAMs
C DMA Access
(2)
Access
(Byte-Aligned)
(1)
(Bytes)
(x16 Aligned)
(2)
no
2008 A000 – 2008 BFFF
S1 RAM - Parity Bits
8K
0004 D000 – 0004 DFFF
no
no
2008 C000 – 2008 DFFF
S2 RAM - Parity Bits
8K
0004 E000 – 0004 EFFF
no
no
2008 E000 – 2008 FFFF
S3 RAM - Parity Bits
8K
0004 F000 – 0004 FFFF
no
no
2009 0000 – 2009 1FFF
S4 RAM - Parity Bits
8K
0005 0000 – 0005 0FFF
no
no
2009 2000 – 2009 3FFF
S5 RAM - Parity Bits
8K
0005 1000 – 0005 1FFF
no
no
2009 4000 – 2009 5FFF
S6 RAM - Parity Bits
8K
0005 2000 – 0005 2FFF
no
no
2009 6000 – 2009 7FFF
S7 RAM - Parity Bits
8K
0005 3000 – 0005 3FFF
no
no
2009 8000 – 2009 9FFF
C4 RAM - Parity Bits
8K
no
2009 A000 – 2009 BFFF
C5 RAM - Parity Bits
8K
no
2009 C000 – 2009 DFFF
C6 RAM - Parity Bits
8K
no
2009 E000 – 2009 FFFF
C7 RAM - Parity Bits
8K
no
200A 0000 – 200A 1FFF
C8 RAM - Parity Bits
8K
no
200A 2000 – 200A 3FFF
C9 RAM - Parity Bits
8K
no
200A 4000 – 200A 5FFF
C10 RAM - Parity Bits
8K
no
200A 6000 – 200A 7FFF
C11 RAM - Parity Bits
8K
no
200A 8000 – 200A 9FFF
C12 RAM - Parity Bits
8K
no
200A A000 – 200A BFFF
C13 RAM - Parity Bits
8K
no
200A C000 – 200A DFFF
C14 RAM - Parity Bits
8K
no
200A E000 – 200A FFFF
C15 RAM - Parity Bits
8K
200B 0000 – 200F EFFF
Reserved
no
200F F000 – 200F F7FF
CtoM MSG RAM - Parity Bits
2K
0007 F800 – 0007 FBFF
no
no
200F F800 – 200F FFFF
MtoC MSG RAM - Parity Bits
2K
0007 FC00 – 0007 FFFF
no
2010 0000 – 21FF FFFF
Reserved
Bit Banded RAM Zone
(Dedicated address for each
(Dedicated address for each
yes
2200 0000 – 23FF FFFF
32M
RAM bit of Cortex-M3 RAM
blocks above)
blocks above)
All RAM Spaces – Mirror-
Mapped for µCRC.
Accessing this memory by the
µCRC peripheral will cause an
access to
2000 0000 – 23FF FFFF
Mapped for µCRC.
Accessing this memory by the
µCRC peripheral will cause an
access to
2000 0000 – 23FF FFFF
yes
2400 0000 – 27FF FFFF
64M
memory space.
(Read cycles from this space
cause the µCRC peripheral to
continuously update data
checksum inside a register
when reading a block of data.)
(Read cycles from this space
cause the µCRC peripheral to
continuously update data
checksum inside a register
when reading a block of data.)
2800 0000 – 3FFF FFFF
Reserved
Copyright © 2012–2014, Texas Instruments Incorporated
Device Overview
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