Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 Datenbogen
Produktcode
TMDSADAP180TO100
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
McBSP features include:
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Full-duplex communication
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Double-buffered transmission and triple-buffered reception, allowing a continuous data stream
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Independent clocking and framing for reception and transmission
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The capability to send interrupts to the CPU and to send DMA events to the DMA controller
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128 channels for transmission and reception
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Multichannel selection modes that enable or disable block transfers in each of the channels
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Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected A/D and D/A devices
connected A/D and D/A devices
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Support for external generation of clock signals and frame-synchronization signals
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A programmable sample rate generator for internal generation and control of clock signals and frame
synchronization signals
synchronization signals
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Programmable polarity for frame-synchronization pulses and clock signals
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Direct interface to:
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T1/E1 framers
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IOM-2 compliant devices
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AC97-compliant devices (the necessary multi-phase frame capability is provided)
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I2S compliant devices
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SPI devices
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A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits
NOTE
A value of the chosen data size is referred to as a serial word or word in this section.
Elsewhere, word is used to describe a 16-bit value.
Elsewhere, word is used to describe a 16-bit value.
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µ-law and A-law companding
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The option of transmitting/receiving 8-bit data with the LSB first
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Status bits for flagging exception/error conditions
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ABIS mode is not supported
shows the C28x McBSP peripheral.
Copyright © 2012–2014, Texas Instruments Incorporated
Peripheral Information and Timings
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