Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 Datenbogen
Produktcode
TMDSADAP180TO100
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
3.12 Control Subsystem Clocking
The CLKIN input clock to the C28x processor is normally a divided-down output of the Main PLL or X1
external clock input. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT,
SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the
C28x processor has read access. The C28x can request write access to the above registers through the
CLKREQEST register. The Cortex-M3 can regain write ownership of these registers through the
MCLKREQUEST register.
external clock input. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT,
SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the
C28x processor has read access. The C28x can request write access to the above registers through the
CLKREQEST register. The Cortex-M3 can regain write ownership of these registers through the
MCLKREQUEST register.
Individual C28x peripherals can be turned on or off by gating C28SYSCLK to those peripherals, which is
done via the CPCLKCR0,2,3 registers.
done via the CPCLKCR0,2,3 registers.
The C28x processor outputs two clocks: C28CPUCLK and C28SYSCLK. The C28SYSCLK is used by
C28x peripherals, C28x Timer 0, C28x Timer 1, and C28x Timer 2. C28x Timer 2 can also be clocked by
OSCCLK or 10MHZCLK (see
C28x peripherals, C28x Timer 0, C28x Timer 1, and C28x Timer 2. C28x Timer 2 can also be clocked by
OSCCLK or 10MHZCLK (see
). The C28CPUCLK is used by the C28x CPU, FPU, VCU, and
PIE.
The Control Subsystem operates in one of three modes: Normal Mode, IDLE Mode, or STANDBY Mode.
shows the Control Subsystem low-power modes and their effect on the C28x CPU, clocks, and
peripherals.
shows the Control Subsystem clocks and low-power modes.
Table 3-27. Control Subsystem Low-Power Modes
(1)
Registers Used to Gate
C28x Low-Power Mode
State of C28x CPU
C28CPUCLK
(2)
C28SYSCLK
(3)
Clocks to C28x
Peripherals
Normal
Active
On
On
CPCLKCR0,1,3
IDLE
Stopped
Off
On
CPCLKCR0,1,3
STANDBY
Stopped
Off
Off
N/A
(1)
The input clock to the C28x CPU is PLLSYSCLK from the Master Subsystem. This clock is turned off when the Master Subsystem
enters the Deep Sleep mode.
enters the Deep Sleep mode.
(2)
C28CPUCLK is an output from the C28x CPU. C28CPUCLK clocks the C28x FPU, VCU, and PIE.
(3)
C28SYSCLK is an output from the C28x CPU. C28SYSCLK clocks C28x peripherals.
3.12.1 C28x Normal Mode
In Normal Mode, the C28x processor, Local Memory, and C28x peripherals are clocked by the
C28SYSCLK, which is derived from the C28CLKIN input clock to the C28x processor. The FPU, VCU, and
PIE are clocked by the C28CPUCLK, which is also derived from the C28CLKIN. Timer 2 can also be
clocked by the TMR2CLK, which is a divided-down version of one of three source clocks—C28SYSCLK,
OSCCLK, and 10MHZCLK—as selected by the CLKCTL register. Additionally, the LOSPCP register can
be programmed to provide a dedicated clock (C28LSPCLK) to the SCI, SPI, and McBSP peripherals.
C28SYSCLK, which is derived from the C28CLKIN input clock to the C28x processor. The FPU, VCU, and
PIE are clocked by the C28CPUCLK, which is also derived from the C28CLKIN. Timer 2 can also be
clocked by the TMR2CLK, which is a divided-down version of one of three source clocks—C28SYSCLK,
OSCCLK, and 10MHZCLK—as selected by the CLKCTL register. Additionally, the LOSPCP register can
be programmed to provide a dedicated clock (C28LSPCLK) to the SCI, SPI, and McBSP peripherals.
Clock gating for individual peripherals is defined inside the CPCLKCR0,1,3 registers. Execution of the
IDLE instruction stops the C28x processor from clocking and activates the IDLES signal. The IDLES
signal is gated with two LPM bits of the CPCLKCR0 register to enter the C28x Subsystem into IDLE mode
or STANDBY Mode.
IDLE instruction stops the C28x processor from clocking and activates the IDLES signal. The IDLES
signal is gated with two LPM bits of the CPCLKCR0 register to enter the C28x Subsystem into IDLE mode
or STANDBY Mode.
3.12.2 C28x IDLE Mode
In IDLE Mode, the C28x processor stops executing instructions and the C28CPUCLK is turned off. The
C28SYSCLK continues to run. Exit from IDLE Mode is accomplished by any enabled interrupt or the
C28NMIINT (C28x non-maskable interrupt).
C28SYSCLK continues to run. Exit from IDLE Mode is accomplished by any enabled interrupt or the
C28NMIINT (C28x non-maskable interrupt).
Upon exit from IDLE Mode, the C28CPUCLK is restored. If LPMWAKE interrupt is enabled, the
LPMWAKE ISR is executed. Next, the C28x processor starts fetching instructions from a location
immediately following the IDLE instruction that originally triggered the IDLE Mode.
LPMWAKE ISR is executed. Next, the C28x processor starts fetching instructions from a location
immediately following the IDLE instruction that originally triggered the IDLE Mode.
60
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