Texas Instruments CDCM6208V1 Evaluation Module CDCM6208V1EVM CDCM6208V1EVM Datenbogen
Produktcode
CDCM6208V1EVM
Using the EVM Control Software
6.3
Input MUX Selection
The CDCM6208 employs a smart MUX selecting the input clock for the PLL. The input clock is either
primary reference only, secondary reference only, or in automatic selection mode. Toggling the connection
line, the proper reference input is selected. If the Auto box is selected, automatic input selection mode is
activated.
primary reference only, secondary reference only, or in automatic selection mode. Toggling the connection
line, the proper reference input is selected. If the Auto box is selected, automatic input selection mode is
activated.
6.4
Input Divider (M) For the PLL Selection
The input (M) divider is a continuous 14-b counter (1–16384) that is present after the Smart Input MUX.
The output of the M divider sets the PFD frequency to the PLL and must be in the range of 8 kHz to 100
MHz.
The output of the M divider sets the PFD frequency to the PLL and must be in the range of 8 kHz to 100
MHz.
6.5
Charge Pump Current Selection
The charge-pump current value is chosen from the pull-down menu. The allowable range of the charge-
pump current is from 500 µA to 4 mA.
pump current is from 500 µA to 4 mA.
6.6
Loop Filter (3
rd
Pole only) Selection
C1, R2, and C2 are external loop filter components connected to the ELF pin, but the 3
rd
pole of the loop
filter is internal to the device with R3 and C3 register-selectable. Appropriate C3 and R3 values are
selected using the pull-down menu.
selected using the pull-down menu.
6.7
Feedback Divider Selection
The feedback divider (N) is made up of a cascaded 8-b counter divider (1–256) and a 10-b counter divider
(1–1024) present on the feedback path of the PLL. If the divider value is available, the software
automatically selects the proper combination from the two cascaded dividers. The output of the N divider
sets the PFD frequency to the PLL and must be in the range of 8 kHz to 100 MHz.
(1–1024) present on the feedback path of the PLL. If the divider value is available, the software
automatically selects the proper combination from the two cascaded dividers. The output of the N divider
sets the PFD frequency to the PLL and must be in the range of 8 kHz to 100 MHz.
6.8
Prescalar Dividers (PS_A and PS_B) Selection
The prescaler (PS) dividers are fed by the output of the VCO and are distributed to the output dividers
(PS_A to the dividers for outputs Y0, Y1, Y4, and Y5. PS_B to the dividers for outputs Y2, Y3, Y6, and
Y7). PS_A also completes the PLL, driving the input of the feedback divider (N). Appropriate values are
set for each prescalar using the pull-down menu.
(PS_A to the dividers for outputs Y0, Y1, Y4, and Y5. PS_B to the dividers for outputs Y2, Y3, Y6, and
Y7). PS_A also completes the PLL, driving the input of the feedback divider (N). Appropriate values are
set for each prescalar using the pull-down menu.
6.9
VCO Frequency Selection
The VCO frequency value depends on the selection of reference input frequency and input dividers,
prescalar (PS_A), and feedback dividers. The software automatically calculates the VCO frequency, based
on the selection, and provides the value. If the calculated VCO frequency is outside of the range, it flashs
red.
prescalar (PS_A), and feedback dividers. The software automatically calculates the VCO frequency, based
on the selection, and provides the value. If the calculated VCO frequency is outside of the range, it flashs
red.
6.10 Output MUX Selection
Both Y4 and Y5 outputs have multiplexers which select one of the three inputs (PRI_REF, SEC_REF, or
PS_A) for the outputs. The proper input is selected for the outputs by dragging the connection line.
PS_A) for the outputs. The proper input is selected for the outputs by dragging the connection line.
6.11 Output Dividers
Outputs Y0 and Y1 share one 8-bit continuous integer divider and outputs Y2 and Y3 share another 8-bit
continuous integer divider; therefore, these pairs of outputs have the same frequency. Each of the outputs
Y4, Y5, Y6, and Y7 have 8-bit continuous integer dividers and in addition, 20-bit fractional dividers. The
software automatically chooses the right divider values for Y4–Y7 outputs from the integer and fractional
dividers, if the expected output frequency in the desired output box is provided.
continuous integer divider; therefore, these pairs of outputs have the same frequency. Each of the outputs
Y4, Y5, Y6, and Y7 have 8-bit continuous integer dividers and in addition, 20-bit fractional dividers. The
software automatically chooses the right divider values for Y4–Y7 outputs from the integer and fractional
dividers, if the expected output frequency in the desired output box is provided.
6
CDCM6208 Evaluation Board
SCAU049A – May 2012 – Revised January 2013
Copyright © 2012–2013, Texas Instruments Incorporated