Texas Instruments TPS65131EVM Evaluation Module TPS65131EVM-063 TPS65131EVM-063 Datenbogen
Produktcode
TPS65131EVM-063
Input/Output Connector Descriptions
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1.1
Performance Specification Summary
All specifications are given for an ambient temperature of 25°C. Although the EVM operates with input
voltages over the 2.5 V to 5.5 V recommended operating input voltage range of the TPS65131 IC, the
power supply designs on the EVM were optimized for an input voltage of 3.3 V ± 10%. The wide voltage
range of VNEG is due to the 5%, 1.3-M
voltages over the 2.5 V to 5.5 V recommended operating input voltage range of the TPS65131 IC, the
power supply designs on the EVM were optimized for an input voltage of 3.3 V ± 10%. The wide voltage
range of VNEG is due to the 5%, 1.3-M
Ω
feedback resistor. A 1% feedback resistor would tighten the
VNEG range to: -12.4 V to -11.6 V.
Table 1. Typical Performance Specification Summary
VOLTAGE RANGE (V)
CURRENT RANGE (mA)
CONDITION
MIN
TYP
MAX
MIN
TYP
MAX
VIN
3
3.3
3.6
5000
VPOS
V
I
= 3.3 V
11.6
12
12.4
410
VNEG
V
I
= 3.3 V
-13.1
-12
-11.2
165
1.2
Modifications
To demonstrate the small size of this power solution, the EVM is designed with components having 0402
footprints where possible, and small inductors. Changing components either improves or degrades EVM
performance. For example, using an inductor with smaller dc resistance may improve efficiency of the
solution. When populated with a 0-
footprints where possible, and small inductors. Changing components either improves or degrades EVM
performance. For example, using an inductor with smaller dc resistance may improve efficiency of the
solution. When populated with a 0-
Ω
resistor, resistor R9 shorts out transistor Q1, thereby removing the
load-disconnect feature of the IC. Resistors R10 and R11 are for test purposes only. They can be
replaced by a 51.1 to 100 ohm resistor to assist in taking a loop gain measurement with a loop gain
analyzer. R10 and R11 will not be needed in the end application.
replaced by a 51.1 to 100 ohm resistor to assist in taking a loop gain measurement with a loop gain
analyzer. R10 and R11 will not be needed in the end application.
2
Input/Output Connector Descriptions
J1
−
VIN This is the positive connection to the input power supply. The leads to the input supply should be
twisted and kept as short as possible.
J2
−
GND This is the return connection to the input power supply.
J3
−
VPOS This is the positive output of the device.
J4
−
GND This is the return connection for the load on the positive converter of the device.
J5
−
VNEG This is the negative output of the device.
J6
−
GND This is the return connection for the load on the negative converter of the device.
JP1
−
ENP This is the enable pin for the positive converter (VPOS). Placing a jumper across pins 2
−
3 of
JP1 shorts the enable pin to GND, thereby disabling the device. Placing a jumper across pins 1
−
2 of JP1
connects the enable pin to Vin and enables the device.
JP2
−
PSP This is the control pin for the power-save mode of the positive converter. Placing a jumper
across pins 2
−
3 of JP2 shorts the pin to GND, thereby disabling the power-save mode. Placing a jumper
across pins 1
−
2 of JP2 connects the pin to VI, thereby enabling the power-save mode.
JP3
−
ENN This is the enable pin for the negative converter (VNEG). Placing a jumper across pins 2
−
3 of
JP3 shorts the enable pin to GND, thereby disabling the device. Placing a jumper across pins 1
−
2 of JP3
connects the enable pin to Vin and enables the device.
JP4
−
PSN This is the control pin for the power-save mode of the negative converter. Placing a jumper
across pins 2
−
3 of JP4 shorts the pin to GND, thereby disabling the power-save mode. Placing a jumper
across pins 1
−
2 of JP4 connects the pin to V
I
, thereby enabling the power-save mode.
2
TPS65131EVM User's Guide
SLVU119C – February 2005 – Revised December 2010
© 2005–2010, Texas Instruments Incorporated