Texas Instruments LV32EVK01 Evaluation Kit LV32EVK01/NOPB LV32EVK01/NOPB Datenbogen
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LV32EVK01/NOPB
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Configuration Settings for the Deserializer Board
S1: Deserializer Input Features Selection
Reference
Description
Input = L
Input = H
S1
RSVD
ReSerVeD
MUST be
tied low for
normal
operation
tied low for
normal
operation
(Default)
Not allowed
RRFB
Latch input data on Rising
or Falling edge of
RxCLKOUT
or Falling edge of
RxCLKOUT
Falling Edge
(Default)
Rising Edge
PWDNB
PoWerDowN Bar Power
Down
(Disabled)
Normal
Operational
Operational
(Default)
REN
Receiver Output Data
ENabled
ENabled
Disabled Enabled
(Default)
Output Monitor Pins for the Deserializer Board
JP3: Output Lock Monitor
Reference
Description
Output = L
Output = H
JP3
LOCK Receiver
PLL LOCK Status
Note:
DO NOT PUT A SHORTING
JUMPER IN JP3.
DO NOT PUT A SHORTING
JUMPER IN JP3.
Unlocked PLL
LOCKED
(LED1 will
illuminate)
illuminate)
National Semiconductor Corporation
Date: 9/28/2009
Page 11 of 34
Page 11 of 34