Texas Instruments DS99R124Q-EVK FPD-Link II to FPD-Link Converter Evaluation Kit DS99R124Q-EVK/NOPB DS99R124Q-EVK/NOPB Datenbogen

 

 

                                

 

 
© National Semiconductor Corporation 2009 

 

                                          Printed in U.S.  

3

 

 

J7 

5V DC 

Optional 5V DC Power Jack (Not Populated)  

J4 

1.8V DC 

1.8V VDD Power. 

JP1 

3.3V DC 

3.3V VDD Power. 

J5 VSS 

Ground. 

JP2 

VDDIO 

Connect to 3.3V or 1.8V. 

JP3 

VDDA2 

Always connect to 1.8V. 

- 

VDDPC 

Always connect to 1.8V. 

- 

VDDL 

Always connect to 1.8V. 

-  

VDDTXC 

Always connect to 3.3V. 

J8 

20 position wall 

header 

Connect to FPD-Link output. 

J1 

Automotive HSD 

Connector 

Connect to FPD-Link II input (default). 

J9 and J10 

SMA Connector 

Connect to FPD-Link II input. 
(When using these connectors, R3 and R4 should be placed with 0Ω resistors, the traces 
from R3 and R4 to the J1 should be cut). 

J2 USB 

Connector 

Connect to FPD-Link II input. 
(When using this connector,  P1 should be removed, and R24 and R25 should be placed 
with 0Ω resistors) 

JP12 and JP13 

Power Wire in USB 
cable through J2 

Connect to VSS is recommended. 

JP4 

TESTEN 

NSC test mode. Always connect it to “L” or leave it unconnected.  

JP5 

LF_MODE 

Connect to “L” or “H” for the PCLK frequency select. See datasheet for detail information. 

JP6 

OSSEL 

Connect to “L” or “H” for the Output State select. See datasheet for detail information. 

JP7 OEN 

Connect it to “L” or “H” for the FPD Link Output Enable. See datasheet for detail 
information. 

JP8 VODSEL 

Connect it to “L” or “H” for the FPD-Link VOD level select. See datasheet for detail 
information. 

JP9 

BISTM 

Connect it to “L” or “H” for the BIST Mode. See datasheet for detail information. 

JP10 

BISTEN 

Connect it to “H” for the BIST enable mode. See datasheet for detail information. 

- PDB 

Connect it to “L” for the power down mode. Connect it to “H” for the enable mode.  
See datasheet for detail information. 

- 

SSC[2:0] 

Connect them to “L” or “H” for the SSCG selection. 

- OS[2:0] 

Over 

Sample 

Bit 

Outputs 

JP24 and VR3 

ID[x] 

Connect JP24 to VSS to have the default device PHY address (h’DC). 
Connect JP24 to VR3; then adjust VR3 value to select desired device PHY address. See 
datasheet for detail information. 

J3 and JP23 

I2C Interface 

Connect JP23 if the I2C power is not supplied on J6. Otherwise, leave it unconnected. 

LED1 

PASS 

PASS output. “ON” when PASS is “H” 

LED2 

LOCK 

LOCK output. “ON” when LOCK is “H” 

JP11, JP25 

Other options 

Do not connect