Texas Instruments PCM4202 Evaluation Module PCM4202EVM PCM4202EVM Datenbogen
Produktcode
PCM4202EVM
www.ti.com
3.6
Digital High-Pass Filter
Hardware Description and Configuration
Table 4. Sampling Mode Selection: PCM Slave Mode Audio Formats
FS2
FS1
FS0
Sampling Mode
LO
LO
LO
Single Rate with Clock Auto-Detection
LO
LO
HI
Dual Rate with Clock Auto-Detection
LO
HI
LO
Quad Rate with Clock Auto-Detection
LO
HI
HI
Reserved
HI
LO
LO
Reserved
HI
LO
HI
Reserved
HI
HI
LO
Reserved
HI
HI
HI
Reserved
Table 5. Sampling Mode Selection: PCM Master Mode Audio Formats
FS2
FS1
FS0
Sampling Mode
LO
LO
LO
Single Rate with f
SCKI
= 768f
S
LO
LO
HI
Single Rate with f
SCKI
= 512f
S
LO
HI
LO
Single Rate with f
SCKI
= 384f
S
LO
HI
HI
Single Rate with f
SCKI
= 256f
S
HI
LO
LO
Dual Rate with f
SCKI
= 384f
S
HI
LO
HI
Dual Rate with f
SCKI
= 256f
S
HI
HI
LO
Quad Rate with f
SCKI
= 192f
S
HI
HI
HI
Quad Rate with f
SCKI
= 128f
S
Table 6. Sampling Mode Selection: DSD Output Mode
FS2
FS1
FS0
Sampling Mode
LO
LO
LO
128f
s
DSD Output Rate with f
SCKI
= 768f
S
LO
LO
HI
128f
s
DSD Output Rate with f
SCKI
= 512f
S
LO
HI
LO
128f
s
DSD Output Rate with f
SCKI
= 384f
S
LO
HI
HI
128f
s
DSD Output Rate with f
SCKI
= 256f
S
HI
LO
LO
64f
s
DSD Output Rate with f
SCKI
= 384f
S
HI
LO
HI
64f
s
DSD Output Rate with f
SCKI
= 256f
S
HI
HI
LO
Reserved
HI
HI
HI
Reserved
The PCM4202 includes a digital high-pass filter function for both channels, designed for removing
the DC component from the digitized signal. The high-pass filter is not available when using the
DSD output mode. The high-pass filter function may be enabled or disabled using the HPFD switch
on SW1.
Table 7
summarizes the operation of the HPFD switch.
Table 7. Digital High-Pass Filter Configuration
HPFD
Digital High-Pass Filter Function
LO
Enabled
HI
Disabled
PCM4202EVM User's Guide
SBAU103–August 2004
11