Texas Instruments DP130 Single-Source Evaluation Module DP130SSEVM DP130SSEVM Datenbogen
Produktcode
DP130SSEVM
SLLSE57D – APRIL 2011 – REVISED JULY 2013
Table 4. AUX and DDC Interface Configurations
I
2
C
I
2
C
AUX
HPD_SNK
CAD_SNK
AUX_SNK
AUX_SRC
DDC
COMMENT
REGISTER
REGISTER
MONITOR
BIT 04.0
BIT 04.1
0
X
X
X
OFF
OFF
OFF
inactive
no sink detected; low power mode
0
DP sink detected; AUX_SNK connects to
0
ON
ON
OFF
active
(default; works
AUX_SRC
for Intel,
TMDS cable adapter detected; DDC
NVIDIA, and
1
ON
OFF
ON
inactive
connects to AUX_SNK
AMD)
0
DP sink detected; AUX_SNK disconnected
(default)
0
OFF
ON
OFF
active
from AUX_SRC; AUX_SNK monitors AUX
1
training
(NVIDIA, AMD
1
TMDS cable adapter detected; AUX_SNK
special mode)
1
ON
ON
OFF
inactive
connects to AUX_SRC and can be used to
short AC coupling caps
short AC coupling caps
DP sink detected; AUX_SNK connects to
0
active
AUX_SRC
0
ON
ON
OFF
1
TMDS cable adapter detected; AUX_SRC
1
inactive
connects to AUX_SNK
1
undetermined
mode not recommended
MAIN LINK EQ CONFIGURATION DETAILS
The EQ input stage is self-configuring based on Link Training. A variety of EQ settings are available through
external pin configuration to accommodate for different PCB loss and GPU settings, and the I
external pin configuration to accommodate for different PCB loss and GPU settings, and the I
2
C interface may be
utilized to fully customize EQ configuration lane-by-lane beyond the input pin configurability options, as described
in
in
.
Table 5. Main Link EQ Configurations
LINK
CAD_SNK
(1)
LINK TRAINING
EQ_I2C_ENABLE
TRAINING
LINK TRAINING AEQ(Lx)
(2)
ADDR_EQ
VIL = DP
AEQ(Lx)
(2)
DESCRIPTION
(reg 05.7)
ON/OFF
LANE 0 to 2
VIH = TMDS
LANE 3
(reg 04.2)
AEQ(L0) = 8dB at 2.7GHz
automatic low-range EQ gain
AEQ(L1) = 6dB at 2.7GHz
1 (default)
based on link training; DP
AEQ(L2) = 3.5dB at 2.7GHz
VIL
same as Lane 0 to 2
mode
AEQ(L3) = 0dB at 2.7GHz
VIL
0
AEQ(Lx) = 6dB at 2.7GHz
DP mode; fixed EQ
VIH
x
EQ(Lx) = 6dB at 2.7GHz
3dB at 1.35GHz
TMDS mode; fixed EQ
1
AEQ(Lx) = 8dB at 2.7GHz
DP mode; fixed EQ
VIL
same as Lane 0 to 2
0 (default)
VIM
0
AEQ(Lx) = 8dB at 2.7GHz
DP mode; fixed EQ
VIH
x
EQ(Lx) = 8dB at 2.7GHz
3dB at 1.35GHz
TMDS mode; fixed EQ
AEQ(L0) = 15dB at 2.7GHz
automatic high-range EQ gain
AEQ(L1) = 13dB at 2.7GHz
1
based on link training; DP
AEQ(L2) = 10dB at 2.7GHz
VIL
same as Lane 0 to 2
mode
AEQ(L3) = 6dB at 2.7GHz
VIH
0
AEQ(Lx) = 13dB at 2.7GHz
DP mode; fixed EQ
VIH
x
EQ(Lx) = 13dB at 2.7GHz
3dB at 1.35GHz
TMDS mode; fixed EQ
DP mode; EQ fully
AEQ(Lx) = 0dB at 2.7GHz
programmable for each
1
training level; EQ disabled by
AEQ(Lx) I
2
C programmable
default
VIL
same as Lane 0 to 2
1
x
DP mode; EQ fully
programmable by AEQ(L1)
0
AEQ(L1) = 0dB at 2.7GHz
levels; default AEQ(L1) EQ
AEQ(L1) I
2
C programmable
setting at 6dB At 2.7GHz
VIH
x
3dB at 1.35GHz
TMDS mode; fixed EQ
(1)
Setting CAD_TEST_MODE (Reg 17.0) forces the SN75DP130 into a TMDS test mode even if no external CAD signal is present
(2)
EQ setting is adjusted based on the output pre-emphasis level setting; the EQ setting is indifferent to the level of V
OD
.
24
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