Texas Instruments TMDSEMU560V2STM-U - Blackhawk XDS560v2 System Trace USB Emulator TMDSEMU560V2STM-U TMDSEMU560V2STM-U Datenbogen
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TMDSEMU560V2STM-U
XDS560 Emulator Cable Pod Signal Timing
3-10
3.6.1
Emulation Timing Calculations
The following examples help you calculate emulation timings in your system.
For actual target timing parameters, see the appropriate device data sheet.
For actual target timing parameters, see the appropriate device data sheet.
Assumptions:
t
su(TTMS)
Setup time, target TMS/TDI before TCK high
10 ns
t
pd(TTDO)
Delay time, TCK low to valid target TDO
15 ns
t
pd(bufmax)
Delay time, target buffer – maximum
10 ns
t
pd(bufmin)
Delay time, target buffer – minimum
1 ns
T
bufskew)
Skew time, target buffer between two devices in the same pack-
age: [t
age: [t
d(bufmax)
– t
d(bufmin)
]
⋅
0.15
1.35 ns
T
(TCKfactor)
40/60 clock duty cycle
0.4(40%)
Given in Table 3−5:
t
d(TMSmax)
Delay time, emulator TMS/TDI valid from TCK_RET high
31 ns
t
su(TDOmin)
Setup time, TDO before emulator TCK_RET high, minimum
2.5 ns
There are two key timing paths to consider in the emulation design:
-
The TCK_RET-to-TMS/TDI path, called
t
pd(TCK_RET–TMS/TDI)
, and
-
The TCK_RET-to-TDO path, called
t
pd(TCK_RET–TDO)
.
Of the following two cases (Equation 3−1 and Equation 3−2), the worst-case
path delay is calculated to determine the maximum system test clock
frequency.
path delay is calculated to determine the maximum system test clock
frequency.
Equation 3−1. Key Timing Path Case 1
Case 1: Single processor, direct connection, TMS/TDI timed from
TCK_RET high.
TCK_RET high.
t
pdĂǒTCK_RET*TMSńTDIǓ
Ă +Ă t
pdĂ(TMSmax)
) t
suĂ(TTMS)
+Ă 31Ăns ) 10Ăns
+Ă 41ĂnsĂ(24.4ĂMHz)