Texas Instruments The ADC12DC105 is a dual 12-Bit, 105 Msps A/D Converter ADC12DC105LFEB/NOPB ADC12DC105LFEB/NOPB Datenbogen
Produktcode
ADC12DC105LFEB/NOPB
SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008
Functional Description
Operating on a single +3.0V or +3.3V supply, the ADC12DC105 digitizes two differential analog input signals to
12 bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold
circuit to ensure maximum performance. The user has the choice of using an internal 1.2V stable reference, or
using an external 1.2V reference. Any external reference is buffered on-chip to ease the task of driving that pin.
Duty cycle stabilization and output data format are selectable using the quad state function OF/DCS pin (pin 19).
The output data can be set for offset binary or two's complement.
12 bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold
circuit to ensure maximum performance. The user has the choice of using an internal 1.2V stable reference, or
using an external 1.2V reference. Any external reference is buffered on-chip to ease the task of driving that pin.
Duty cycle stabilization and output data format are selectable using the quad state function OF/DCS pin (pin 19).
The output data can be set for offset binary or two's complement.
APPLICATIONS INFORMATION
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC12DC105:
2.7V
≤
V
A
≤
3.6V
2.4V
≤
V
DR
≤
V
A
20 MHz
≤
f
CLK
≤
105 MHz
1.2V internal reference
V
REF
= 1.2V (for an external reference)
V
CM
= 1.5V (from V
CMO
)
ANALOG INPUTS
Signal Inputs
Differential Analog Input Pins
The ADC12DC105 has a pair of analog signal input pins for each of two channels. V
IN
+ and V
IN
−
form a
differential input pair. The input signal, V
IN
, is defined as:
V
IN
= (V
IN
+) – (V
IN
−
)
(10)
shows the expected input signal range. Note that the common mode input voltage, V
CM
, should be
1.5V. Using V
CMO
(pins 7,9) for V
CM
will ensure the proper input common mode level for the analog input signal.
The positive peaks of the individual input signals should each never exceed 2.6V. Each analog input pin of the
differential pair should have a maximum peak-to-peak voltage of 1V, be 180° out of phase with each other and
be centered around V
differential pair should have a maximum peak-to-peak voltage of 1V, be 180° out of phase with each other and
be centered around V
CM
.The peak-to-peak voltage swing at each analog input pin should not exceed the 1V or
the output data will be clipped.
Figure 18. Expected Input Signal Range
Copyright © 2008, Texas Instruments Incorporated
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