Texas Instruments CDCLVD2106 Evaluation Module CDCLVD2106EVM CDCLVD2106EVM Datenbogen
Produktcode
CDCLVD2106EVM
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Output Clock
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Output Clock
The CDCLVD1212 and CDCLVD2106 generate up to 12 LVDS outputs and 4 outputs are available on the
EVM (OUT0, OUT5, OUT6 and OUT11) through the following SMAs: J5 and J6 for OUT0; J7 and J8 for
OUT5; J9 and J10 for OUT6; J11 and J12 for OUT11. The LVDS outputs are AC coupled to the
respective SMAs. Each output pair has an option of 100
EVM (OUT0, OUT5, OUT6 and OUT11) through the following SMAs: J5 and J6 for OUT0; J7 and J8 for
OUT5; J9 and J10 for OUT6; J11 and J12 for OUT11. The LVDS outputs are AC coupled to the
respective SMAs. Each output pair has an option of 100
Ω
termination on the board (R12, R13, R18 and
R19 – not populated).
All other outputs have test points.
CDCLVD2106: Using the control pin EN (labeled as JPM1), outputs can be disabled or enabled.
Table 1. Output Control for CDCLVD2106
EN (JMP1)
CLOCK OUTPUTS
0 (GND)
All outputs disabled (static "0")
OPEN
All outputs enabled
1 (VDD)
OUT0, OUT5 enabled and OUT6, OUT11 disabled (static “0”)
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EVM Board Schematic and Bill of Materials
9.1
EVM Board Schematic
Figure 2. CDCLVD1212/CDCLVD2106EVM – Schematic (Page 1 of 3)
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SCAU045 – September 2010
Low Additive Jitter, Twelve LVDS Outputs Clock Buffer Evaluation Board
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