Texas Instruments SRC4382 Evaluation Module (EVM) and USB motherboard SRC4382EVM-PDK SRC4382EVM-PDK Datenbogen
Produktcode
SRC4382EVM-PDK
www.ti.com
NOTE: See Figure 82 for power-supply connections. Da
ptional connections to the host.
shed lines denote o
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BCKA
LRCKA
SDINA
SDOUTA
NC
VIO
DGND3
BGND
SDOUTB
SDINB
LRCKB
BCKB
RX1+
RX1
-
RX2+
RX2
-
RX3+
RX3
-
RX4+
RX4
-
VCC
AGND
LOCK
RXCKO
SYNC
BLS
AESOUT
VDD33
TX+
TX
-
DGND2
GPO4
GPO3
GPO2
GPO1
MCLK
RST
INT
CDOUT
CDIN
CCLK
CS
CPM
VDD18
DGND1
RDY
MUTE
RXCKI
SRC4382IPFB
From Digita Inpu
l
ts
(Line, Optical, Logic)
To Digital Outputs
(L ne,
i
O
ca
L
pti
l,
ogic)
To Host o Exter al
r
n
Logic
To Host or
xternal
E
Logic
SPI
Host
Controller
Audio
I/O
Device
Audio
I/O
Device
DIR
Ref Clock
Master
Clock
DIR Recovered Clock
VIO
10k
W
NOTE: See Figure 82 for power-supply connections. Da
ptional connect on
o
e host.
shed lines denote o
i
t
s t
h
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1
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2
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9
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BCKA
LR KA
C
SDI A
N
SDOUTA
NC
VIO
DGND3
BGND
SDOUTB
SDI B
N
LR KB
C
BCKB
RX +
1
RX
-
1
RX +
2
RX
-
2
RX +
3
RX
-
3
RX +
4
RX
-
4
VCC
AGND
LOCK
RX KO
C
SYNC
BLS
AESO T
U
VDD 3
3
TX+
TX
-
DGND2
GP
4
O
GP
3
O
GP
2
O
GP
1
O
MCLK
RST
INT
SDA
A1
SCL
A0
CPM
VDD 8
1
DGND1
RDY
MUTE
RX KI
C
SRC4382IPFB
From Digital Inputs
(Line, Optica , Log
l
ic)
To Digital Outputs
(Line, Optical, Logic)
To Host or Exte nal
r
Logic
To Host or Exte nal
r
Logic
I C
2
Ho t
s
Controller
Audio
I/O
Device
Audio
I/O
Device
DIR
Ref Clock
Master
Clock
DIR Recovered Clock
VIO
10k
W
2.7k
W
Tie
LO or HI
SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007
Figure 80. Typical Application Diagram Using SPI Host Interface
Figure 81. Typical Application Diagram Using I
2
C Host Interface
Copyright © 2006–2007, Texas Instruments Incorporated
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