Texas Instruments DP83849IFVS Basic product evaluation and customer demo board with FX DP83849IFVS-EVK/NOPB DP83849IFVS-EVK/NOPB Datenbogen
Produktcode
DP83849IFVS-EVK/NOPB
October 2006
Tung Ngo
v1.1
National Semiconductor Corp
4
Table of jumpers:
Jumper
Name
Function
Setting
Power
J8
J8
MII 5V/3V3
Select 5V or 3.3V from MII connector
Jumpered
J10
MII port selection
Select MII voltage from Port A/B
Jumpered
J23
3V3 _LP3964
Use 3V3 from the voltage regulator
Jumpered
J91
POE Connector
Allow 48Vfrom a PSE. Requires a separate baby board.
Open
J92
MII_3V3
Enable voltage from MII to the board
Jumpered
Reset
J4
J4
RESET_N
Allow external RESET
Open
MDIO/MDC Access
J1
J1
MDIO/MDC
Allow MDIO/MDC signals connect from MII (SmartBits) to Port A/B
Jumpered
J26
uMDIO
Allow the Integrity Interface connect to the device.
Open
Address
J36
J36
PHYAD1
Phy Addresses strap pin
Open
J37
PHYAD2
Phy Addresses strap pin
Open
Auto-Negotiation
J42
J42
ANEN_B
Port B – Enable/Disable Auto Negotiation
Jumpered
J43
AN1_B
Port B – Forced/Advertised Operation Mode in Auto Negotiation
Jumpered
J44
AN0_B
Port B – Forced/Advertised Operation Mode in Auto Negotiation
Jumpered
J45
AN0_A
Port A – Forced/Advertised Operation Mode in Auto Negotiation
Jumpered
J46
AN1_A
Port A – Forced/Advertised Operation Mode in Auto Negotiation
Jumpered
J47
ANEN_A
Port A – Enable/Disable Auto Negotiation
Jumpered
Function
J40
J40
EXTENDER_EN
Allow Extender Mode (For DP83849IVS/IFVS )
Open
J41
CLK2MAC_DIS
Disable Clock to MAC output
Jumpered
J48
PWRDOWN_INT_B
Port B – Allow Power Down and Interrupt Mode
Open
J49
ED_EN_B
Port B – Enable Energy Detect Mode
Open
J50
FX_EN_B
Port B – Enable Fiber Mode (For DP83849IDVS/IFVS)
Jumpered
J51
MDIX_EN_B
Port B – Enable/Disable MDIX Mode (Default is Enabling)
Open
J52
LED_CFG_B
Port B – Allow LEDs configuration. See datasheet
Open
J55
LED_CFG_A
Port A – Allow LEDs configuration. See datasheet
Open
J56
MDIX_EN_A
Port A – Enable/Disable MDIX Mode (Default is Enabling)
Open
J57
ED_EN_A
Port A – Enable Energy Detect Mode
Open
J58
PWRDOWN_INT_A
Port A – Allow Power Down and Interrupt Mode
Open
Interface
J2
J2
JTAG pins
JTAG interface (For DP83849IVS/IDVS/IFVS)
J7
MII Header
Port B – Allow connection to MII pins
J9
MII Male Connector
Port B – SmartBits interface
J13
MII Header
Port A – Allow connection to MII pins
J14
MII Male Connector
Port A – SmartBits interface
J84
Connector
Port B – RJ-45 connector
J85
Connector
Port A – RJ-45 connector
J89
FX transceiver
Port B – HP FX transceiver (HFBR5803). Not stuffed in copper configuration
J90
CLK2MAC
Clock output. Not stuffed
J93
Integrity Interface
Allow access to the device with National Integrity Software
Additional information for all options above may be found in the DP83849IFVS datasheet.