Texas Instruments TAS2505 Evaluation Module TAS2505EVM TAS2505EVM Datenbogen
Produktcode
TAS2505EVM
T0146-09
WCLK
BCLK
DIN
t (WS)
d
t (WS)
d
t (DI)
S
t (DI)
h
t
f
t
r
SLAS778A – FEBRUARY 2013 – REVISED FEBRUARY 2013
3.5.3
DSP Timing in Master Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.
IOVDD = 1.8 V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
d
(WS)
WCLK delay
45
45
ns
t
s
(DI)
DIN setup
8
6
ns
t
h
(DI)
DIN hold
8
6
ns
t
r
Rise time
25
10
ns
t
f
Fall time
25
10
ns
Figure 3-3. DSP Timing in Master Mode
Copyright © 2013, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
11
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