Texas Instruments TPS54262EVM Evaluation Module TPS54262EVM TPS54262EVM Datenbogen
Produktcode
TPS54262EVM
Board Layout
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JP4 to 200ms
In this configuration, the device will power up when power is applied.
JP1 LPM selects how Low Power Mode is set, Enabled or Disabled. JP2 ENA turns the device on or off.
JP3 SR selects the Slew Rate for the switch pin, 1V/2.5ns, 1V/4ns, 1V/6ns or 1V/1.2ns. JP4 Delay selects
the reset delay time for the device, 2.2ms, 47ms, 150ms or 200ms.
JP3 SR selects the Slew Rate for the switch pin, 1V/2.5ns, 1V/4ns, 1V/6ns or 1V/1.2ns. JP4 Delay selects
the reset delay time for the device, 2.2ms, 47ms, 150ms or 200ms.
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Board Layout
and
show the board layout for the TPS54262EVM PWB. The EVM offers
resistors, capacitors and jumpers to program the switch pin Slew Rate and regulator turn on Delay.
Jumpers are also provided to Enable the device and to enable the Low Power Mode option.
Jumpers are also provided to Enable the device and to enable the Low Power Mode option.
The TPS54262 converter offers high efficiency, but does dissipate power. The PowerPAD™ package
offers an exposed thermal pad to enhance thermal performance. This must be soldered to the copper
landing on the PCB for optimal performance. The PCB provides 1 oz copper planes on the top and bottom
to dissipate heat.
offers an exposed thermal pad to enhance thermal performance. This must be soldered to the copper
landing on the PCB for optimal performance. The PCB provides 1 oz copper planes on the top and bottom
to dissipate heat.
Figure 5. Top Assembly Layer
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TPS54262EVM
SLVU344 – October 2009
Copyright © 2009, Texas Instruments Incorporated