Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
5.7
Correctable Error Mask Register
The correctable error mask register controls the reporting of individual errors as they occur. When a mask
bit is set to 1b, the corresponding error status bit is not set, PCIe error messages are blocked, the header
log is not loaded, and the first error pointer is not updated. See
bit is set to 1b, the corresponding error status bit is not set, PCIe error messages are blocked, the header
log is not loaded, and the first error pointer is not updated. See
for a complete description of the
register contents.
PCIe extended register
114h
offset:
Register type:
Read only, Read/Write
Default value:
0000 2000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-6. Correctable Error Mask Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:14
RSVD
R
Reserved. Returns 000 0000 0000 0000 0000b when read.
13
ANFEM
RW
Advisory nonfatal error mask
0 = Error condition is unmasked.
1 = Error condition is masked (default).
1 = Error condition is masked (default).
12
(1)
REPLAY_TMOUT_MASK
RW
Replay timer time-out mask
0 = Error condition is unmasked (default).
1 = Error condition is masked.
1 = Error condition is masked.
11:9
RSVD
R
Reserved. Returns 000b when read.
8
(1)
REPLAY_ROLL_MASK
RW
REPLAY_NUM rollover mask
0 = Error condition is unmasked (default).
1 = Error condition is masked.
1 = Error condition is masked.
7
(1)
BAD_DLLP_MASK
RW
Bad DLLP error mask
0 = Error condition is unmasked (default).
1 = Error condition is masked.
1 = Error condition is masked.
6
(1)
BAD_TLP_MASK
RW
Bad TLP error mask
0 = Error condition is unmasked (default).
1 = Error condition is masked.
1 = Error condition is masked.
5:1
RSVD
R
Reserved. Returns 00000b when read.
0
(1)
RX_ERROR_MASK
RW
Receiver error mask
0 = Error condition is unmasked (default).
1 = Error condition is masked.
1 = Error condition is masked.
(1)
These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
102
PCIe Extended Configuration Space
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