Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
5.13 Secondary Error Capabilities and Control Register
The secondary error capabilities and control register allows the system to monitor and control the
secondary advanced error reporting capabilities. See
secondary advanced error reporting capabilities. See
for a complete description of the register
contents.
PCIe extended register offset:
138h
Register type:
Read only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-11. Secondary Error Capabilities and Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:5
RSVD
R
Reserved. Return 000 0000 0000 0000 0000 0000 0000b when read.
4:0
(1)
SEC_FIRST_ERR
RU
First error pointer. This 5-bit value reflects the bit position within the secondary
uncorrectable error status register (offset12Ch, see
uncorrectable error status register (offset12Ch, see
) corresponding to the
class of the first error condition that was detected.
(1)
These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
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PCIe Extended Configuration Space
107
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