Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
7.5
Class Code and Revision ID Registers
The class code and revision ID registers categorize the 1394b OHCI controller as a serial bus controller
(0Ch), controlling an IEEE Std 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the
TI chip revision is indicated in the least significant byte. See
(0Ch), controlling an IEEE Std 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the
TI chip revision is indicated in the least significant byte. See
for a complete description of the
register contents.
PCI register offset:
08h
Register type:
Read only
Default value:
0C00 1001h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
Table 7-4. Class Code and Revision ID Registers Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31-24
BASECLASS
R
Base class. This field returns 0Ch when read, which broadly classifies the function as a
serial bus controller.
serial bus controller.
23-16
SUBCLASS
R
Subclass. This field returns 00h when read, which specifically classifies the function as
controlling an IEEE Std 1394 serial bus.
controlling an IEEE Std 1394 serial bus.
15-8
PGMIF
R
Programming interface. This field returns 10h when read, which indicates that the
programming model is compliant with the 1394 Open Host Controller Interface
Specification.
programming model is compliant with the 1394 Open Host Controller Interface
Specification.
7-0
CHIPREV
R
Silicon revision. This field returns 00h when read, which indicates the silicon revision of the
1394b OHCI controller.
1394b OHCI controller.
7.6
Cache Line Size and Latency Timer Registers
The latency timer and class cache line size registers are programmed by the host BIOS to indicate system
cache-line size and the latency timer are associated with the 1394b OHCI controller. See
cache-line size and the latency timer are associated with the 1394b OHCI controller. See
for a
complete description of the register contents.
PCI register offset:
0Ch
Register type:
Read/Write
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 7-5. Latency Timer and Class Cache Line Size Registers Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15-8
LATENCY_TIMER
RW
PCI latency timer. The value in this register specifies the latency timer for the 1394b OHCI
controller, in units of PCI clock cycles. When the 1394b OHCI function is a PCI bus
initiator and asserts PCI_FRAME, the latency timer begins counting from zero. If the
latency timer expires before the 1394b OHCI functions transaction has terminated, the
1394b OHCI function terminates the transaction when its PCI_GNT is deasserted.
controller, in units of PCI clock cycles. When the 1394b OHCI function is a PCI bus
initiator and asserts PCI_FRAME, the latency timer begins counting from zero. If the
latency timer expires before the 1394b OHCI functions transaction has terminated, the
1394b OHCI function terminates the transaction when its PCI_GNT is deasserted.
7-0
CACHELINE_SZ
RW
Cache-line size. This value is used by the OHCI controller during memory write and
invalidate, memory-read line, and memory-read multiple transactions. The default value for
this field is 00h.
invalidate, memory-read line, and memory-read multiple transactions. The default value for
this field is 00h.
118
1394 OHCI PCI Configuration Space
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