Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
Table 8-16. Interrupt Mask Register Description (continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
24
unrecoverableError
RSC
When this bit and bit 24 (unrecoverableError) in the interrupt event register at OHCI offset
80h/84h (see
80h/84h (see
) are set to 11b, this unrecoverable-error interrupt mask enables
interrupt generation.
23
cycleInconsistent
RSC
When this bit and bit 23 (cycleInconsistent) in the interrupt event register at OHCI offset
80h/84h (see
80h/84h (see
) are set to 11b, this inconsistent-cycle interrupt mask enables
interrupt generation.
22
cycleLost
RSC
When this bit and bit 22 (cycleLost) in the interrupt event register at OHCI offset 80h/84h (see
) are set to 11b, this lost-cycle interrupt mask enables interrupt generation.
21
cycle64Seconds
RSC
When this bit and bit 21 (cycle64Seconds) in the interrupt event register at OHCI offset
80h/84h (see
80h/84h (see
) are set to 11b, this 64-s cycle interrupt mask enables interrupt
generation.
20
cycleSynch
RSC
When this bit and bit 20 (cycleSynch) in the interrupt event register at OHCI offset 80h/84h
(see
(see
) are set to 11b, this isochronous-cycle interrupt mask enables interrupt
generation.
19
phy
RSC
When this bit and bit 19 (phy) in the interrupt event register at OHCI offset 80h/84h (see
) are set to 11b, this PHY-status-transfer interrupt mask enables interrupt
generation.
18
regAccessFail
RSC
When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h
(see
(see
) are set to 11b, this register-access-failed interrupt mask enables interrupt
generation.
17
busReset
RSC
When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see
) are set to 11b, this bus-reset interrupt mask enables interrupt generation.
16
selfIDcomplete
RSC
When this bit and bit 16 (selfIDcomplete) in the interrupt event register at OHCI offset 80h/84h
(see
(see
) are set to 11b, this self-ID-complete interrupt mask enables interrupt
generation.
15
selfIDcomplete2
RSC
When this bit and bit 15 (selfIDcomplete2) in the interrupt event register at OHCI offset
80h/84h (see
80h/84h (see
) are set to 11b, this second self-ID-complete interrupt mask
enables interrupt generation.
14-10
RSVD
R
Reserved. Bits 14-10 return 00000b when read.
9
lockRespErr
RSC
When this bit and bit 9 (lockRespErr) in the interrupt event register at OHCI offset 80h/84h
(see
(see
) are set to 11b, this lock-response-error interrupt mask enables interrupt
generation.
8
postedWriteErr
RSC
When this bit and bit 8 (postedWriteErr) in the interrupt event register at OHCI offset 80h/84h
(see
(see
) are set to 11b, this posted-write-error interrupt mask enables interrupt
generation.
7
isochRx
RSC
When this bit and bit 7 (isochRx) in the interrupt event register at OHCI offset 80h/84h (see
) are set to 11b, this isochronous-receive-DMA interrupt mask enables interrupt
generation.
6
isochTx
RSC
When this bit and bit 6 (isochTx) in the interrupt event register at OHCI offset 80h/84h (see
) are set to 11b, this isochronous-transmit-DMA interrupt mask enables interrupt
generation.
5
RSPkt
RSC
When this bit and bit 5 (RSPkt) in the interrupt event register at OHCI offset 80h/84h (see
) are set to 11b, this receive-response-packet interrupt mask enables interrupt
generation.
4
RQPkt
RSC
When this bit and bit 4 (RQPkt) in the interrupt event register at OHCI offset 80h/84h (see
) are set to 11b, this receive-request-packet interrupt mask enables interrupt
generation.
3
ARRS
RSC
When this bit and bit 3 (ARRS) in the interrupt event register at OHCI offset 80h/84h (see
) are set to 11b, this asynchronous-receive-response-DMA interrupt mask enables
interrupt generation.
2
ARRQ
RSC
When this bit and bit 2 (ARRQ) in the interrupt event register at OHCI offset 80h/84h (see
) are set to 11b, this asynchronous-receive-request-DMA interrupt mask enables
interrupt generation.
1
respTxComplete
RSC
When this bit and bit 1 (respTxComplete) in the interrupt event register at OHCI offset 80h/84h
(see
(see
) are set to 11b, this response-transmit-complete interrupt mask enables
interrupt generation.
0
reqTxComplete
RSC
When this bit and bit 0 (reqTxComplete) in the interrupt event register at OHCI offset 80h/84h
(see
(see
) are set to 11b, this request-transmit-complete interrupt mask enables
interrupt generation.
Copyright © 2008–2013, Texas Instruments Incorporated
1394 OHCI Memory-Mapped Register Space
151
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