Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM Datenbogen
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XIO2213BEVM
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
4.23 Prefetchable Base Upper 32 Bits Register
This read/write register specifies the upper 32 bits of the prefetchable memory base register. See
for a complete description of the register contents.
PCI register offset:
28h
Register type:
Read/Write
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-14. Prefetchable Base Upper 32 Bits Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:0
PREBASE
RW
Prefetchable memory base upper 32 bits. Defines the upper 32 bits of the lowest address of the
prefetchable memory address range that determines when to forward memory transactions
downstream.
prefetchable memory address range that determines when to forward memory transactions
downstream.
4.24 Prefetchable Limit Upper 32 Bits Register
This read/write register specifies the upper 32 bits of the prefetchable memory limit register. See
for a complete description of the register contents.
PCI register offset:
2Ch
Register type:
Read/Write
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-15. Prefetchable Limit Upper 32 Bits Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:0
PRELIMIT
RW
Prefetchable memory limit upper 32 bits. Defines the upper 32 bits of the highest address of the
prefetchable memory address range that determines when to forward memory transactions
downstream.
prefetchable memory address range that determines when to forward memory transactions
downstream.
60
Classic PCI Configuration Space
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